Simulation Results: uart

 
14/09/2026 15:31:43 DVSim: v1.53.0 sha: f87cc85 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 93.45 %
  • code
  • 92.53 %
  • assert
  • 97.12 %
  • func
  • 90.69 %
  • block
  • 98.83 %
  • line
  • 99.24 %
  • branch
  • 97.79 %
  • toggle
  • 73.08 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.000s 513.176us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 48.226us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 47.624us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 4.000s 269.766us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 17.462us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 2.000s 66.186us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 47.624us 1 1 100.00
uart_csr_aliasing 1.000s 17.462us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 38.000s 41622.118us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.000s 513.176us 1 1 100.00
uart_tx_rx 38.000s 41622.118us 1 1 100.00
parity_error 2 2 100.00
uart_intr 29.000s 49629.806us 1 1 100.00
uart_rx_parity_err 12.000s 13178.166us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 38.000s 41622.118us 1 1 100.00
uart_intr 29.000s 49629.806us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 30.000s 40158.287us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 76.000s 78748.149us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 68.000s 53778.727us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 29.000s 49629.806us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 29.000s 49629.806us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 29.000s 49629.806us 1 1 100.00
perf 1 1 100.00
uart_perf 44.000s 17335.748us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 1.000s 87.678us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 1.000s 87.678us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 15.000s 9207.030us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 6.000s 1775.317us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 16.000s 6810.149us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 30.000s 4608.132us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 199.000s 109966.170us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 216.000s 107596.593us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 13.654us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 2.000s 16.987us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 3.000s 45.993us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 3.000s 45.993us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 48.226us 1 1 100.00
uart_csr_rw 1.000s 47.624us 1 1 100.00
uart_csr_aliasing 1.000s 17.462us 1 1 100.00
uart_same_csr_outstanding 2.000s 50.589us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 48.226us 1 1 100.00
uart_csr_rw 1.000s 47.624us 1 1 100.00
uart_csr_aliasing 1.000s 17.462us 1 1 100.00
uart_same_csr_outstanding 2.000s 50.589us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 38.279us 1 1 100.00
uart_tl_intg_err 2.000s 76.994us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 2.000s 76.994us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 20.000s 4716.338us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:376) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 1 test run
uart_noise_filter 83274907482068272945355804514667696457149401000488347704827376215626184344886 87
UVM_ERROR @ 8603342825 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 8603342825 ps: (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 8721792825 ps: (uart_scoreboard.sv:499) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 2 (+/-1), act: 6, clk_pulses: 0
UVM_ERROR @ 8721930325 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (212 [0xd4] vs 249 [0xf9]) reg name: uart_reg_block.rdata