Simulation Results: ac_range_check

 
15/09/2026 15:31:43 DVSim: v1.53.0 sha: 2e7b496 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 82.88 %
  • code
  • 93.06 %
  • assert
  • 97.75 %
  • func
  • 57.84 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 81.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 32.000s 511.036us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 59.000s 11510.961us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 9.000s 94.981us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 10.000s 263.290us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 37.000s 731.693us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 13.000s 429.769us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 10.000s 91.662us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 10.000s 263.290us 1 1 100.00
ac_range_check_csr_aliasing 13.000s 429.769us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 10.000s 28.526us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 39.000s 5530.891us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 259.000s 16817.149us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 9.000s 16.172us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 9.000s 42.308us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 44.663us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 44.663us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 9.000s 94.981us 1 1 100.00
ac_range_check_csr_rw 10.000s 263.290us 1 1 100.00
ac_range_check_csr_aliasing 13.000s 429.769us 1 1 100.00
ac_range_check_same_csr_outstanding 7.000s 598.756us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 9.000s 94.981us 1 1 100.00
ac_range_check_csr_rw 10.000s 263.290us 1 1 100.00
ac_range_check_csr_aliasing 13.000s 429.769us 1 1 100.00
ac_range_check_same_csr_outstanding 7.000s 598.756us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 18.000s 2105.816us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 18.000s 2105.816us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 18.000s 2105.816us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 18.000s 2105.816us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 87.000s 5937.439us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 2.000s 20.882us 1 1 100.00
ac_range_check_tl_intg_err 8.000s 343.757us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 241.000s 1224.570us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 30.000s 5963.886us 1 1 100.00