Simulation Results: aes/gcm_masked

 
15/09/2026 15:31:43 DVSim: v1.53.0 sha: 2e7b496 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 85.96 %
  • code
  • 95.55 %
  • assert
  • 98.43 %
  • func
  • 63.91 %
  • block
  • 96.35 %
  • line
  • 97.41 %
  • branch
  • 91.27 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
94.74%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 107.795us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 237.868us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 203.328us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 113.244us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 671.183us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 117.901us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 3.000s 137.188us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 113.244us 1 1 100.00
aes_csr_aliasing 3.000s 117.901us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 237.868us 1 1 100.00
aes_config_error 5.000s 388.840us 1 1 100.00
aes_stress 13.000s 935.282us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 237.868us 1 1 100.00
aes_config_error 5.000s 388.840us 1 1 100.00
aes_stress 13.000s 935.282us 1 1 100.00
back2back 2 2 100.00
aes_stress 13.000s 935.282us 1 1 100.00
aes_b2b 19.000s 797.281us 1 1 100.00
backpressure 1 1 100.00
aes_stress 13.000s 935.282us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 237.868us 1 1 100.00
aes_config_error 5.000s 388.840us 1 1 100.00
aes_stress 13.000s 935.282us 1 1 100.00
aes_alert_reset 9.000s 300.077us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 58.879us 1 1 100.00
aes_config_error 5.000s 388.840us 1 1 100.00
aes_alert_reset 9.000s 300.077us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 6.000s 110.206us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 9.000s 281.242us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 11.000s 1537.291us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 9.000s 300.077us 1 1 100.00
stress 1 1 100.00
aes_stress 13.000s 935.282us 1 1 100.00
sideload 2 2 100.00
aes_stress 13.000s 935.282us 1 1 100.00
aes_sideload 4.000s 67.626us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 4.000s 115.513us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 7.000s 331.197us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 4.000s 286.674us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 3.000s 157.016us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 97.976us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 97.976us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 203.328us 1 1 100.00
aes_csr_rw 2.000s 113.244us 1 1 100.00
aes_csr_aliasing 3.000s 117.901us 1 1 100.00
aes_same_csr_outstanding 3.000s 320.390us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 203.328us 1 1 100.00
aes_csr_rw 2.000s 113.244us 1 1 100.00
aes_csr_aliasing 3.000s 117.901us 1 1 100.00
aes_same_csr_outstanding 3.000s 320.390us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 5.000s 118.529us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 5.000s 283.338us 0 1 0.00
aes_control_fi 20.000s 10019.971us 0 1 0.00
aes_cipher_fi 2.000s 65.594us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 3.000s 92.766us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 3.000s 92.766us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 3.000s 92.766us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 3.000s 92.766us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 373.815us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 10.000s 3278.139us 1 1 100.00
aes_tl_intg_err 3.000s 200.732us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 200.732us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 9.000s 300.077us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 92.766us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 92.766us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 237.868us 1 1 100.00
aes_stress 13.000s 935.282us 1 1 100.00
aes_alert_reset 9.000s 300.077us 1 1 100.00
aes_core_fi 6.000s 240.168us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 4.000s 286.674us 1 1 100.00
aes_config_error 5.000s 388.840us 1 1 100.00
aes_stress 13.000s 935.282us 1 1 100.00
aes_core_fi 6.000s 240.168us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 92.766us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 92.290us 1 1 100.00
aes_stress 13.000s 935.282us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 13.000s 935.282us 1 1 100.00
aes_sideload 4.000s 67.626us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 92.290us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 92.290us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 92.290us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 92.290us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 92.290us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 13.000s 935.282us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 13.000s 935.282us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 5.000s 283.338us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 5.000s 283.338us 0 1 0.00
aes_control_fi 20.000s 10019.971us 0 1 0.00
aes_cipher_fi 2.000s 65.594us 1 1 100.00
aes_ctr_fi 3.000s 66.144us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 5.000s 283.338us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 5.000s 283.338us 0 1 0.00
aes_control_fi 20.000s 10019.971us 0 1 0.00
aes_cipher_fi 2.000s 65.594us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 65.594us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 5.000s 283.338us 0 1 0.00
sec_cm_ctr_fsm_redun 1 3 33.33
aes_fi 5.000s 283.338us 0 1 0.00
aes_control_fi 20.000s 10019.971us 0 1 0.00
aes_ctr_fi 3.000s 66.144us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 5.000s 283.338us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 5.000s 283.338us 0 1 0.00
aes_control_fi 20.000s 10019.971us 0 1 0.00
aes_cipher_fi 2.000s 65.594us 1 1 100.00
aes_ctr_fi 3.000s 66.144us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 9.000s 300.077us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 5.000s 283.338us 0 1 0.00
aes_control_fi 20.000s 10019.971us 0 1 0.00
aes_cipher_fi 2.000s 65.594us 1 1 100.00
aes_ctr_fi 3.000s 66.144us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 5.000s 283.338us 0 1 0.00
aes_control_fi 20.000s 10019.971us 0 1 0.00
aes_cipher_fi 2.000s 65.594us 1 1 100.00
aes_ctr_fi 3.000s 66.144us 1 1 100.00
sec_cm_ctr_fsm_local_esc 1 3 33.33
aes_fi 5.000s 283.338us 0 1 0.00
aes_control_fi 20.000s 10019.971us 0 1 0.00
aes_ctr_fi 3.000s 66.144us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_ghash_fi 3.000s 84.216us 1 1 100.00
aes_fi 5.000s 283.338us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 5.000s 283.338us 0 1 0.00
aes_control_fi 20.000s 10019.971us 0 1 0.00
aes_cipher_fi 2.000s 65.594us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 4.000s 210.676us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_stress_all 79269540193937058208297145451783556920570624974821177614695749873224845898819 22903
UVM_INFO @ 331197472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 2864282251777205459422155451794315172034914257377415279929470200541867316331 148
UVM_INFO @ 210676115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 45999201533002458273847518720790529904290666893265053513804431223627753961695 14207
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 2
----| Expected corrupted: 0
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 1 test run
aes_control_fi 27790255551077424943899485454330587970366039226799339260021332228600238466859 153
UVM_INFO @ 10019971471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---