Simulation Results: alert_handler

 
15/09/2026 15:31:43 DVSim: v1.53.0 sha: 2e7b496 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.42 %
  • code
  • 88.99 %
  • assert
  • 98.29 %
  • func
  • 68.97 %
  • line
  • 99.70 %
  • branch
  • 97.84 %
  • cond
  • 90.54 %
  • toggle
  • 81.07 %
  • FSM
  • 75.81 %
Validation stages
V1
100.00%
V2
78.95%
V2S
75.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 64.460s 1196.745us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 5.090s 76.872us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 4.330s 146.461us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 171.480s 1390.452us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 151.830s 3610.699us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 6.500s 104.468us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 4.330s 146.461us 1 1 100.00
alert_handler_csr_aliasing 151.830s 3610.699us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 54.860s 789.801us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 36.030s 2637.899us 1 1 100.00
entropy 0 1 0.00
alert_handler_entropy 3600.127s 0.000us 0 1 0.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 21.300s 1774.352us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 64.460s 1196.745us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 46.520s 3334.915us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 12.290s 618.772us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 14.140s 242.496us 0 1 0.00
lpg 1 2 50.00
alert_handler_lpg 381.330s 57017.361us 0 1 0.00
alert_handler_lpg_stub_clk 1674.750s 36632.446us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 4244.510s 410871.054us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 5.850s 172.599us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 3.340s 131.546us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.570s 14.550us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 8.600s 388.233us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 8.600s 388.233us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 5.090s 76.872us 1 1 100.00
alert_handler_csr_rw 4.330s 146.461us 1 1 100.00
alert_handler_csr_aliasing 151.830s 3610.699us 1 1 100.00
alert_handler_same_csr_outstanding 18.300s 250.195us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 5.090s 76.872us 1 1 100.00
alert_handler_csr_rw 4.330s 146.461us 1 1 100.00
alert_handler_csr_aliasing 151.830s 3610.699us 1 1 100.00
alert_handler_same_csr_outstanding 18.300s 250.195us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 197.950s 2603.230us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 197.950s 2603.230us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 197.950s 2603.230us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 197.950s 2603.230us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 764.080s 9571.909us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 14.140s 926.664us 1 1 100.00
alert_handler_tl_intg_err 109.090s 1317.310us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 109.090s 1317.310us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 197.950s 2603.230us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 64.460s 1196.745us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 64.460s 1196.745us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 64.460s 1196.745us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 64.460s 1196.745us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 21.300s 1774.352us 1 1 100.00
sec_cm_lpg_intersig_mubi 0 1 0.00
alert_handler_lpg 381.330s 57017.361us 0 1 0.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 21.300s 1774.352us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 0 1 0.00
alert_handler_entropy 3600.127s 0.000us 0 1 0.00
sec_cm_esc_tx_intersig_bkgn_chk 0 1 0.00
alert_handler_entropy 3600.127s 0.000us 0 1 0.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 14.140s 926.664us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 14.140s 926.664us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 14.140s 926.664us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 14.140s 926.664us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 14.140s 926.664us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 14.140s 926.664us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 14.140s 926.664us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 14.140s 926.664us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 14.140s 926.664us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 35.420s 513.304us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:604) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. 2 test runs
alert_handler_ping_timeout 86057371305589404519733783165963755166607765536589576228191888192935520730137 86
UVM_INFO @ 242495843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_lpg 24103416617014159138762126543269796100522698615406896053229308371514987688625 86
UVM_INFO @ 57017361298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
alert_handler_entropy 98611944722085861666271524892801267022505825336074232590583510328885605803522 None
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 49514713976538707855667631179050762980893673732438119755793797413127082634577 204
UVM_INFO @ 172598796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 74937483230187274532727908192316083012676615495825439474510529051873022269169 89
UVM_INFO @ 513303795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---