Simulation Results: clkmgr

 
15/09/2026 15:31:43 DVSim: v1.53.0 sha: 2e7b496 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 74.31 %
  • code
  • 69.70 %
  • assert
  • 90.08 %
  • func
  • 63.14 %
  • line
  • 82.22 %
  • branch
  • 87.53 %
  • cond
  • 79.11 %
  • toggle
  • 99.62 %
  • FSM
  • 0.00 %
Validation stages
V1
66.67%
V2
69.23%
V2S
50.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.320s 57.680us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.280s 25.033us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.200s 39.440us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 1.320s 32.330us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.500s 45.059us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 1.470s 25.654us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 1.200s 39.440us 1 1 100.00
clkmgr_csr_aliasing 1.500s 45.059us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.180s 14.900us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.240s 39.047us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.890s 146.636us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.320s 57.680us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.970s 5.780us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.940s 4.402us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.970s 5.780us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.020s 30.303us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.890s 25.615us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.630s 43.967us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.630s 43.967us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
clkmgr_csr_hw_reset 1.280s 25.033us 1 1 100.00
clkmgr_csr_rw 1.200s 39.440us 1 1 100.00
clkmgr_csr_aliasing 1.500s 45.059us 1 1 100.00
clkmgr_same_csr_outstanding 1.140s 15.379us 0 1 0.00
tl_d_partial_access 3 4 75.00
clkmgr_csr_hw_reset 1.280s 25.033us 1 1 100.00
clkmgr_csr_rw 1.200s 39.440us 1 1 100.00
clkmgr_csr_aliasing 1.500s 45.059us 1 1 100.00
clkmgr_same_csr_outstanding 1.140s 15.379us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 3.750s 167.555us 1 1 100.00
clkmgr_tl_intg_err 0.970s 16.105us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 2.040s 66.120us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 2.040s 66.120us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 2.040s 66.120us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 2.040s 66.120us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.790s 6.654us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.970s 16.105us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.970s 5.780us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.940s 4.402us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 2.040s 66.120us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 2.660s 177.280us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.200s 39.440us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 3.750s 167.555us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.200s 39.440us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.200s 39.440us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 3.750s 167.555us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 1.220s 22.639us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.150s 12.932us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 71377690115651682537237486362756235135265772046905421849155743507401956055810 82
UVM_INFO @ 5780210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 54901764250666726218602539951352072592115479475196368624606278974398957135521 81
UVM_INFO @ 30303486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 7019298877441251605660535705613805588515825091969118761411129276162673902482 84
UVM_INFO @ 4402221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 115036359374622891726799881903069647962244390914845890551603814257775867753820 85
UVM_INFO @ 12932426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 2 test runs
clkmgr_tl_intg_err 56803240842238575981258998792827705333846910998402395006612242523890536103800 88
UVM_INFO @ 16104956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 93552082260732697223106086816301653552353026728022065661298036379640767365790 82
UVM_INFO @ 25654327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed 1 test run
clkmgr_regwen 46677654487405810964204111099308227710409972093145296940655730818296969119155 80
UVM_INFO @ 22638951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 18996984940739271591117437798126760152932761860845716797852086761274628872337 81
UVM_INFO @ 6654307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 2598974090425337767580346198228095667041288492903381862698221924739217151792 81
UVM_INFO @ 32329526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 98626183832224845154750745622690248099342821222457173555608167321982974742475 81
UVM_INFO @ 15378854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---