Simulation Results: dma

 
15/09/2026 15:31:43 DVSim: v1.53.0 sha: 2e7b496 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 83.10 %
  • code
  • 90.41 %
  • assert
  • 96.61 %
  • func
  • 62.29 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 77.37 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 7.000s 1384.080us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 671.156us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 6.000s 1925.177us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 40.934us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 68.513us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 13.000s 3069.338us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 2.000s 135.296us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 23.630us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 68.513us 1 1 100.00
dma_csr_aliasing 2.000s 135.296us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 43.000s 11676.654us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 340.000s 19835.148us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 316.000s 202519.888us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 316.000s 202519.888us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 340.000s 19835.148us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 479.000s 153138.320us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 316.000s 202519.888us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 14.000s 3961.174us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 198.000s 38887.329us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 23.128us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 32.505us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 43.795us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 43.795us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 40.934us 1 1 100.00
dma_csr_rw 2.000s 68.513us 1 1 100.00
dma_csr_aliasing 2.000s 135.296us 1 1 100.00
dma_same_csr_outstanding 3.000s 107.143us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 40.934us 1 1 100.00
dma_csr_rw 2.000s 68.513us 1 1 100.00
dma_csr_aliasing 2.000s 135.296us 1 1 100.00
dma_same_csr_outstanding 3.000s 107.143us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 20.000s 197.590us 1 1 100.00
dma_generic_stress 479.000s 153138.320us 1 1 100.00
dma_handshake_stress 316.000s 202519.888us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 6.000s 677.513us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 2.000s 400.190us 1 1 100.00
dma_sec_cm 2.000s 14.665us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 189.000s 13198.228us 1 1 100.00
dma_longer_transfer 5.000s 514.050us 1 1 100.00
dma_stress_all_with_rand_reset 13.000s 487.278us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1297) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 12752242185325507016108542034329858736109411499236541487453309963912973390899 104
UVM_INFO @ 487277910ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---