Simulation Results: edn/edn1

 
15/09/2026 15:31:43 DVSim: v1.53.0 sha: 2e7b496 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.43 %
  • code
  • 84.28 %
  • assert
  • 98.44 %
  • func
  • 82.56 %
  • line
  • 98.33 %
  • branch
  • 93.72 %
  • cond
  • 90.46 %
  • toggle
  • 95.70 %
  • FSM
  • 43.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.160s 61.974us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.150s 25.377us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.170s 224.894us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.820s 624.824us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.110s 26.636us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.700s 33.216us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.170s 224.894us 1 1 100.00
edn_csr_aliasing 1.110s 26.636us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 3.570s 107.156us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 3.570s 107.156us 1 1 100.00
genbits 1 1 100.00
edn_genbits 3.570s 107.156us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.490s 21.740us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.480s 45.671us 1 1 100.00
errs 1 1 100.00
edn_err 1.310s 19.639us 1 1 100.00
disable 2 2 100.00
edn_disable 1.160s 39.181us 1 1 100.00
edn_disable_auto_req_mode 1.660s 48.406us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 4.320s 3688.789us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.080s 19.846us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.240s 44.661us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.720s 83.078us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.720s 83.078us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.150s 25.377us 1 1 100.00
edn_csr_rw 1.170s 224.894us 1 1 100.00
edn_csr_aliasing 1.110s 26.636us 1 1 100.00
edn_same_csr_outstanding 1.730s 35.375us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.150s 25.377us 1 1 100.00
edn_csr_rw 1.170s 224.894us 1 1 100.00
edn_csr_aliasing 1.110s 26.636us 1 1 100.00
edn_same_csr_outstanding 1.730s 35.375us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.980s 1498.535us 1 1 100.00
edn_tl_intg_err 1.760s 90.888us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.180s 18.297us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.480s 45.671us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.980s 1498.535us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.980s 1498.535us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.980s 1498.535us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.980s 1498.535us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.480s 45.671us 1 1 100.00
edn_sec_cm 4.980s 1498.535us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.480s 45.671us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.760s 90.888us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 79.380s 14462.620us 1 1 100.00