Simulation Results: entropy_src/rng_16bits

 
15/09/2026 15:31:43 DVSim: v1.53.0 sha: 2e7b496 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 69.22 %
  • code
  • 82.21 %
  • assert
  • 73.50 %
  • func
  • 51.96 %
  • block
  • 94.00 %
  • line
  • 97.63 %
  • branch
  • 85.97 %
  • toggle
  • 52.52 %
  • FSM
  • 92.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 3.000s 45.250us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 136.923us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 23.061us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 7.000s 116.876us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 110.133us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
entropy_src_csr_mem_rw_with_rand_reset 3.000s 104.611us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 23.061us 1 1 100.00
entropy_src_csr_aliasing 3.000s 110.133us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 3.000s 45.250us 1 1 100.00
entropy_src_rng 92.000s 14285.145us 1 1 100.00
entropy_src_fw_ov 515.000s 13053.864us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 515.000s 13053.864us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 92.000s 14285.145us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 150.000s 13417.377us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 92.000s 14285.145us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 92.000s 14285.145us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 92.000s 14285.145us 1 1 100.00
entropy_src_intr 3.000s 44.442us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 92.000s 14285.145us 1 1 100.00
entropy_src_functional_alerts 9.000s 593.370us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 4.000s 91.542us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 3.000s 59.753us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 8.000s 511.307us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 30.814us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 127.397us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 6.000s 90.789us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 6.000s 90.789us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 136.923us 1 1 100.00
entropy_src_csr_rw 2.000s 23.061us 1 1 100.00
entropy_src_csr_aliasing 3.000s 110.133us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 46.078us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 136.923us 1 1 100.00
entropy_src_csr_rw 2.000s 23.061us 1 1 100.00
entropy_src_csr_aliasing 3.000s 110.133us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 46.078us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 3.000s 181.994us 1 1 100.00
entropy_src_tl_intg_err 4.000s 181.816us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 92.000s 14285.145us 1 1 100.00
entropy_src_cfg_regwen 2.000s 62.396us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 92.000s 14285.145us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 92.000s 14285.145us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 92.000s 14285.145us 1 1 100.00
entropy_src_fw_ov 515.000s 13053.864us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 59.753us 1 1 100.00
entropy_src_sec_cm 3.000s 181.994us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 59.753us 1 1 100.00
entropy_src_sec_cm 3.000s 181.994us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 92.000s 14285.145us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 59.753us 1 1 100.00
entropy_src_sec_cm 3.000s 181.994us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 59.753us 1 1 100.00
entropy_src_sec_cm 3.000s 181.994us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 3.000s 59.753us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 9.000s 593.370us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 4.000s 181.816us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 481.000s 13030.774us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 8.000s 284.132us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1661) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.alert_test 1 test run
entropy_src_stress_all_with_rand_reset 105476810480413558290994747759208056541740965454421260214784040068224565488631 168
UVM_INFO @ 284132139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---