Simulation Results: hmac

 
15/09/2026 15:31:43 DVSim: v1.53.0 sha: 2e7b496 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 69.81 %
  • code
  • 82.54 %
  • assert
  • 97.17 %
  • func
  • 29.71 %
  • block
  • 97.28 %
  • line
  • 97.99 %
  • branch
  • 93.17 %
  • toggle
  • 45.89 %
  • FSM
  • 93.10 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 7.000s 2551.815us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 42.233us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 54.803us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 6.000s 310.928us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.000s 59.908us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 70.688us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 54.803us 1 1 100.00
hmac_csr_aliasing 2.000s 59.908us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 98.000s 9310.583us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 29.000s 592.874us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 16.000s 2036.453us 1 1 100.00
hmac_test_sha384_vectors 33.000s 1267.972us 1 1 100.00
hmac_test_sha512_vectors 35.000s 327.096us 1 1 100.00
hmac_test_hmac256_vectors 16.000s 3623.336us 1 1 100.00
hmac_test_hmac384_vectors 19.000s 471.002us 1 1 100.00
hmac_test_hmac512_vectors 27.000s 616.472us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 17.000s 839.752us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 253.000s 23073.868us 1 1 100.00
error 1 1 100.00
hmac_error 96.000s 14427.339us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 7.000s 124.741us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 7.000s 2551.815us 1 1 100.00
hmac_long_msg 98.000s 9310.583us 1 1 100.00
hmac_back_pressure 29.000s 592.874us 1 1 100.00
hmac_datapath_stress 253.000s 23073.868us 1 1 100.00
hmac_burst_wr 17.000s 839.752us 1 1 100.00
hmac_stress_all 351.000s 111847.090us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 7.000s 2551.815us 1 1 100.00
hmac_long_msg 98.000s 9310.583us 1 1 100.00
hmac_back_pressure 29.000s 592.874us 1 1 100.00
hmac_datapath_stress 253.000s 23073.868us 1 1 100.00
hmac_wipe_secret 7.000s 124.741us 1 1 100.00
hmac_test_sha256_vectors 16.000s 2036.453us 1 1 100.00
hmac_test_sha384_vectors 33.000s 1267.972us 1 1 100.00
hmac_test_sha512_vectors 35.000s 327.096us 1 1 100.00
hmac_test_hmac256_vectors 16.000s 3623.336us 1 1 100.00
hmac_test_hmac384_vectors 19.000s 471.002us 1 1 100.00
hmac_test_hmac512_vectors 27.000s 616.472us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 7.000s 2551.815us 1 1 100.00
hmac_long_msg 98.000s 9310.583us 1 1 100.00
hmac_back_pressure 29.000s 592.874us 1 1 100.00
hmac_datapath_stress 253.000s 23073.868us 1 1 100.00
hmac_burst_wr 17.000s 839.752us 1 1 100.00
hmac_error 96.000s 14427.339us 1 1 100.00
hmac_wipe_secret 7.000s 124.741us 1 1 100.00
hmac_test_sha256_vectors 16.000s 2036.453us 1 1 100.00
hmac_test_sha384_vectors 33.000s 1267.972us 1 1 100.00
hmac_test_sha512_vectors 35.000s 327.096us 1 1 100.00
hmac_test_hmac256_vectors 16.000s 3623.336us 1 1 100.00
hmac_test_hmac384_vectors 19.000s 471.002us 1 1 100.00
hmac_test_hmac512_vectors 27.000s 616.472us 1 1 100.00
hmac_stress_all 351.000s 111847.090us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 351.000s 111847.090us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 41.240us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 53.789us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 4.000s 37.680us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 4.000s 37.680us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 42.233us 1 1 100.00
hmac_csr_rw 2.000s 54.803us 1 1 100.00
hmac_csr_aliasing 2.000s 59.908us 1 1 100.00
hmac_same_csr_outstanding 2.000s 148.580us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 42.233us 1 1 100.00
hmac_csr_rw 2.000s 54.803us 1 1 100.00
hmac_csr_aliasing 2.000s 59.908us 1 1 100.00
hmac_same_csr_outstanding 2.000s 148.580us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 184.657us 1 1 100.00
hmac_tl_intg_err 6.000s 1183.933us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 6.000s 1183.933us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 7.000s 2551.815us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 4.000s 289.173us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 45.000s 9235.599us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 4.000s 951.119us 1 1 100.00