Simulation Results

Simulation Results: i2c

15/09/2026 15:31:43 DVSim: v1.53.0 sha: 2e7b496 json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
88.21 %

code
86.45 %

assert
96.62 %

func
81.55 %

block
96.33 %

line
95.65 %

branch
93.45 %

toggle
72.52 %

FSM
84.17 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	233.000s	1705.011us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	16.000s	1061.048us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	2.000s	22.700us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	2.000s	27.410us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	5.000s	2541.479us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	87.439us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	2.000s	34.863us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	2.000s	27.410us	1	1	100.00
	i2c_csr_aliasing	2.000s	87.439us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.000s	80.159us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	103.000s	43367.986us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	552.000s	25803.503us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	2.000s	23.820us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3602.138s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	2494.000s	2446.684us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	119.019us	1	1	100.00
	i2c_host_fifo_fmt_empty	9.000s	654.319us	1	1	100.00
	i2c_host_fifo_reset_rx	5.000s	1028.944us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	656.000s	2483.544us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	34.000s	765.247us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	3.000s	266.983us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	5.000s	388.238us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	2800.000s	49391.926us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	12.000s	560.547us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	25.000s	5174.588us	1	1	100.00
	i2c_target_intr_smoke	9.000s	1005.631us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	3.000s	434.763us	1	1	100.00
	i2c_target_fifo_reset_tx	2.000s	2498.359us	1	1	100.00
target_fifo_full				2	3	66.67
	i2c_target_stress_wr	2226.000s	63575.599us	1	1	100.00
	i2c_target_stress_rd	25.000s	5174.588us	1	1	100.00
	i2c_target_intr_stress_wr	3600.000s	0.000us	0	1	0.00
target_timeout				1	1	100.00
	i2c_target_timeout	9.000s	12654.172us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	1126.000s	5229.632us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	9.000s	957.737us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	5.000s	387.588us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	4.000s	501.608us	1	1	100.00
	i2c_target_fifo_watermarks_tx	3.000s	104.192us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	552.000s	25803.503us	1	1	100.00
	i2c_host_perf_precise	11.000s	341.078us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	34.000s	765.247us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.000s	94.122us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	5.000s	529.328us	1	1	100.00
	i2c_target_nack_acqfull_addr	3.000s	467.926us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	794.050us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	8.000s	509.749us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	5.000s	6961.398us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	2.000s	16.171us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	2.000s	42.539us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	4.000s	401.120us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	4.000s	401.120us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	22.700us	1	1	100.00
	i2c_csr_rw	2.000s	27.410us	1	1	100.00
	i2c_csr_aliasing	2.000s	87.439us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	113.847us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	22.700us	1	1	100.00
	i2c_csr_rw	2.000s	27.410us	1	1	100.00
	i2c_csr_aliasing	2.000s	87.439us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	113.847us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	3.000s	536.743us	1	1	100.00
	i2c_sec_cm	1.000s	103.392us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	3.000s	536.743us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	12.000s	485.929us	1
target_error_intr				1
	i2c_target_unexp_stop	4.000s	165.222us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	18.000s	1028.100us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				2 test runs
	i2c_host_fifo_watermark	19335362810213210967857093836815540296727109261116641687954844933743381254198	None
	i2c_target_intr_stress_wr	91071821259731959959015942183892806427021166723708679870696819180440773985409	None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	50309959832161627553145640746275893293767104259490435992083701791497047950295	97	UVM_INFO @ 80159267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	4248552324066201821472907541538485260319306053146290817209855996780545540159	115	UVM_INFO @ 43367985846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	104440901843797853697568231645756161699240152801279444697921928483927137847783	95	UVM_INFO @ 485929057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	52258546688151531274675510455016090630130613513492493500011432200330007613224	128	UVM_INFO @ 1028100019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	102802247423608290297570961785020572736664921636212317081345287672028076905121	93	UVM_INFO @ 388237911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1382) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])				1 test run
	i2c_target_unexp_stop	63876185107122163402330763728994418149727782149730018481693058302600456921320	87	UVM_INFO @ 165221920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---