Simulation Results

Simulation Results: keymgr_dpe/darjeeling

15/09/2026 15:31:43 DVSim: v1.53.0 sha: 2e7b496 json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
65.54 %

code
82.44 %

assert
97.20 %

func
16.99 %

block
97.96 %

line
98.66 %

branch
93.36 %

toggle
56.18 %

FSM
81.54 %

Validation stages

V1		100.00%
V2		100.00%
V2S		100.00%

V1

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	keymgr_dpe_smoke	18.000s	3458.519us	1	1	100.00
csr_hw_reset				1	1	100.00
	keymgr_dpe_csr_hw_reset	2.000s	51.720us	1	1	100.00
csr_rw				1	1	100.00
	keymgr_dpe_csr_rw	2.000s	67.847us	1	1	100.00
csr_bit_bash				1	1	100.00
	keymgr_dpe_csr_bit_bash	14.000s	1034.580us	1	1	100.00
csr_aliasing				1	1	100.00
	keymgr_dpe_csr_aliasing	1.000s	15.243us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	keymgr_dpe_csr_mem_rw_with_rand_reset	2.000s	25.660us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	keymgr_dpe_csr_rw	2.000s	67.847us	1	1	100.00
	keymgr_dpe_csr_aliasing	1.000s	15.243us	1	1	100.00

V2

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
intr_test				1	1	100.00
	keymgr_dpe_intr_test	2.000s	57.641us	1	1	100.00
alert_test				1	1	100.00
	keymgr_dpe_alert_test	2.000s	22.481us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	keymgr_dpe_tl_errors	6.000s	156.498us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	keymgr_dpe_tl_errors	6.000s	156.498us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	keymgr_dpe_csr_hw_reset	2.000s	51.720us	1	1	100.00
	keymgr_dpe_csr_rw	2.000s	67.847us	1	1	100.00
	keymgr_dpe_csr_aliasing	1.000s	15.243us	1	1	100.00
	keymgr_dpe_same_csr_outstanding	2.000s	150.122us	1	1	100.00
tl_d_partial_access				4	4	100.00
	keymgr_dpe_csr_hw_reset	2.000s	51.720us	1	1	100.00
	keymgr_dpe_csr_rw	2.000s	67.847us	1	1	100.00
	keymgr_dpe_csr_aliasing	1.000s	15.243us	1	1	100.00
	keymgr_dpe_same_csr_outstanding	2.000s	150.122us	1	1	100.00

V2S

4/4 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	keymgr_dpe_sec_cm	14.000s	867.225us	1	1	100.00
	keymgr_dpe_tl_intg_err	5.000s	100.035us	1	1	100.00
shadow_reg_update_error				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	61.748us	1	1	100.00
shadow_reg_read_clear_staged_value				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	61.748us	1	1	100.00
shadow_reg_storage_error				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	61.748us	1	1	100.00
shadowed_reset_glitch				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	61.748us	1	1	100.00
shadow_reg_update_error_with_csr_rw				1	1	100.00
	keymgr_dpe_shadow_reg_errors_with_csr_rw	5.000s	276.576us	1	1	100.00
prim_count_check				1	1	100.00
	keymgr_dpe_sec_cm	14.000s	867.225us	1	1	100.00
prim_fsm_check				1	1	100.00
	keymgr_dpe_sec_cm	14.000s	867.225us	1	1	100.00