Simulation Results: lc_ctrl/volatile_unlock_disabled

 
15/09/2026 15:31:43 DVSim: v1.53.0 sha: 2e7b496 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.78 %
  • code
  • 89.64 %
  • assert
  • 95.97 %
  • func
  • 77.74 %
  • block
  • 95.58 %
  • line
  • 96.09 %
  • branch
  • 88.74 %
  • toggle
  • 83.25 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
70.00%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 91.172us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 15.454us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 26.068us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 61.088us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 16.872us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 57.984us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 26.068us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 16.872us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 276.281us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 14.351us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3601.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 5.000s 583.947us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 3.000s 91.501us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 3.000s 207.594us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.000s 438.920us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 65.507us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 189.154us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 22.000s 5694.065us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 1045.683us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 108.613us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 591.058us 1 1 100.00
lc_ctrl_jtag_alert_test 3.000s 44.921us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.000s 922.879us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 36.519us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10802.184s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 137.819us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 4.000s 776.547us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 4.000s 776.547us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 15.454us 1 1 100.00
lc_ctrl_csr_rw 2.000s 26.068us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 16.872us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 46.825us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 15.454us 1 1 100.00
lc_ctrl_csr_rw 2.000s 26.068us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 16.872us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 46.825us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.000s 1326.976us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 136.118us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 136.118us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 276.281us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 5.000s 1326.976us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 5.000s 1326.976us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 5.000s 1326.976us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 5.000s 1326.976us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 5.000s 1326.976us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 5.000s 1326.976us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 5.000s 1326.976us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 5.000s 1326.976us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 583.947us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 11.000s 2707.461us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.000s 8361.400us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.000s 8361.400us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 11 test runs
lc_ctrl_state_failure 58322561969509731979325258406166793399282068472759724744166181948126604040295 None
lc_ctrl_state_post_trans 59870866401313487367655794081681193671433179098753454120654553503346524908983 None
lc_ctrl_prog_failure 61522456814405853191255118981155649046047980203119688769706413484688319837532 None
lc_ctrl_errors 85096010129382812861332758122822277125003554833773455985786345424661139616372 None
lc_ctrl_jtag_state_failure 56724773362658312882148429269565421038372966875024725882675951181444117127722 None
lc_ctrl_jtag_state_post_trans 68075669385331473085126304136008521773066953785025811627840385497733391166370 None
lc_ctrl_jtag_prog_failure 26643666537847520002556694825989218451607745790905617063233280337696266324621 None
lc_ctrl_jtag_errors 86002311098816688542056106921125960093840731774835858252928357571625954141449 None
lc_ctrl_sec_mubi 17270651454863152143765814446300259963897397294212584405871867873683535962906 None
lc_ctrl_stress_all 111737784852110795407997428750581560412852948820824147970369197800981190134039 None
lc_ctrl_stress_all_with_rand_reset 19847402197216322833608948463125419750120819210688619981448205713874350715602 None