Simulation Results: lc_ctrl/volatile_unlock_enabled

 
15/09/2026 15:31:43 DVSim: v1.53.0 sha: 2e7b496 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.05 %
  • code
  • 89.88 %
  • assert
  • 96.54 %
  • func
  • 77.74 %
  • block
  • 96.25 %
  • line
  • 97.12 %
  • branch
  • 90.50 %
  • toggle
  • 79.03 %
  • FSM
  • 92.86 %
Validation stages
V1
100.00%
V2
70.00%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.000s 26.126us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 15.773us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 14.565us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 38.453us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 50.641us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 28.547us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 14.565us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 50.641us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3601.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 560.027us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 14.113us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 8.000s 2628.679us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3601.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 3.000s 270.168us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 9.000s 1185.293us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.000s 2793.227us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 288.204us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 207.281us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 10.000s 2555.768us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 604.885us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 76.107us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 557.850us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 65.756us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.000s 1964.158us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 102.511us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10804.951s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 212.604us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 259.258us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 259.258us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 15.773us 1 1 100.00
lc_ctrl_csr_rw 2.000s 14.565us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 50.641us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 94.972us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 15.773us 1 1 100.00
lc_ctrl_csr_rw 2.000s 14.565us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 50.641us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 94.972us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 175.978us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 52.289us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 52.289us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 560.027us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 175.978us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 175.978us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 175.978us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 175.978us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 175.978us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 175.978us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 175.978us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 175.978us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 8.000s 2628.679us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3601.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3601.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 332.639us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 562.153us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 562.153us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 11 test runs
lc_ctrl_state_failure 73611830373180922656108916533110287187266968408772438731592604154960320117323 None
lc_ctrl_state_post_trans 31239024799684671086752708512458760010258252053318110806086343456214691775121 None
lc_ctrl_prog_failure 67026378230398277788081060291986015222810357134564673646722318867283090269505 None
lc_ctrl_errors 105193902929155633924178028996523464116759326745157291418678484531109964613597 None
lc_ctrl_jtag_state_failure 47000421766119594586683876487560982367384628093932861040476644471944204421936 None
lc_ctrl_jtag_state_post_trans 73037476816324618062405246039121811974609617204012799286215152621197346429361 None
lc_ctrl_jtag_prog_failure 31935773115344234219644901060627182514739274413015293527476592447707975382295 None
lc_ctrl_jtag_errors 87624414282840771426584452209330985325097180266834317429914073802566008395815 None
lc_ctrl_sec_mubi 65663307641678963469290964616977439061637570436536814468365537968786822694183 None
lc_ctrl_stress_all 64989127949530499570946925437132556324664072262442272141297831490120533475933 None
lc_ctrl_stress_all_with_rand_reset 9490847503025252144296888971468771191751457577272201680244875259287346446998 None