Simulation Results: otbn

 
15/09/2026 15:31:43 DVSim: v1.53.0 sha: 2e7b496 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 89.42 %
  • code
  • 81.42 %
  • assert
  • 89.38 %
  • func
  • 97.46 %
  • block
  • 97.71 %
  • line
  • 97.93 %
  • branch
  • 81.44 %
  • toggle
  • 80.13 %
  • FSM
  • 66.20 %
Validation stages
V1
90.00%
V2
88.24%
V2S
96.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 2 50.00
otbn_smoke 12.000s 144.380us 0 1 0.00
otbn_smoke_vectorized 11.000s 21.305us 1 1 100.00
single_binary 1 1 100.00
otbn_single 11.000s 15.860us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 6.000s 84.964us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 5.000s 40.300us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 6.000s 55.342us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 5.000s 40.958us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 9.000s 62.506us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 5.000s 40.300us 1 1 100.00
otbn_csr_aliasing 5.000s 40.958us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 94.000s 4918.809us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 39.000s 573.148us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 74.000s 901.239us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 81.000s 200.918us 1 1 100.00
wfi 1 3 33.33
otbn_wfi_smoke 7.000s 23.391us 0 1 0.00
otbn_wfi_sec_wipe 9.000s 14.222us 1 1 100.00
otbn_wfi_back_to_back 6.000s 17.417us 0 1 0.00
back_to_back 1 1 100.00
otbn_multi 30.000s 51.944us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 73.000s 1004.002us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 9.000s 50.687us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 8.000s 20.790us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 8.000s 51.943us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 7.000s 27.546us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 5.000s 26.222us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 6.000s 116.059us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 6.000s 116.059us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 6.000s 84.964us 1 1 100.00
otbn_csr_rw 5.000s 40.300us 1 1 100.00
otbn_csr_aliasing 5.000s 40.958us 1 1 100.00
otbn_same_csr_outstanding 5.000s 32.700us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 6.000s 84.964us 1 1 100.00
otbn_csr_rw 5.000s 40.300us 1 1 100.00
otbn_csr_aliasing 5.000s 40.958us 1 1 100.00
otbn_same_csr_outstanding 5.000s 32.700us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 14.000s 129.329us 1 1 100.00
otbn_dmem_err 10.000s 21.837us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 11.000s 53.167us 1 1 100.00
otbn_controller_ispr_rdata_err 14.000s 60.298us 1 1 100.00
otbn_mac_bignum_acc_err 17.000s 41.914us 1 1 100.00
otbn_urnd_err 7.000s 10.444us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 10.000s 42.215us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 9.000s 55.776us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 8.000s 112.381us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 261.000s 872.336us 1 1 100.00
otbn_tl_intg_err 27.000s 596.113us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 37.000s 173.151us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 261.000s 872.336us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 261.000s 872.336us 1 1 100.00
sec_cm_mem_scramble 0 1 0.00
otbn_smoke 12.000s 144.380us 0 1 0.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 10.000s 21.837us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 14.000s 129.329us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 27.000s 596.113us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 50.687us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 14.000s 129.329us 1 1 100.00
otbn_dmem_err 10.000s 21.837us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 20.790us 1 1 100.00
otbn_illegal_mem_acc 10.000s 42.215us 1 1 100.00
otbn_sec_cm 261.000s 872.336us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 261.000s 872.336us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 11.000s 15.860us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 14.000s 129.329us 1 1 100.00
otbn_dmem_err 10.000s 21.837us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 20.790us 1 1 100.00
otbn_illegal_mem_acc 10.000s 42.215us 1 1 100.00
otbn_sec_cm 261.000s 872.336us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 261.000s 872.336us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 50.687us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 14.000s 129.329us 1 1 100.00
otbn_dmem_err 10.000s 21.837us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 20.790us 1 1 100.00
otbn_illegal_mem_acc 10.000s 42.215us 1 1 100.00
otbn_sec_cm 261.000s 872.336us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 261.000s 872.336us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 11.000s 15.860us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 10.000s 107.048us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 10.000s 14.113us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 34.000s 476.150us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 34.000s 476.150us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 13.000s 149.180us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 261.000s 872.336us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 261.000s 872.336us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 16.000s 229.413us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 261.000s 872.336us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 261.000s 872.336us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 10.000s 27.782us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 10.000s 27.782us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 6.000s 31.711us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 11.000s 15.860us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 11.000s 15.860us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 11.000s 15.860us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 30.000s 51.944us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 11.000s 15.860us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 11.000s 15.860us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 9.000s 44.786us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 11.000s 15.860us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 261.000s 872.336us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 14.000s 16.760us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:440) [scoreboard] Check failed model_status == * (* [*] vs * [*]) Saw instruction when not in BUSY_EXECUTE operational state. 2 test runs
otbn_wfi_smoke 94417462434663311014777689361082643785252619132148354901672053820612667646446 113
UVM_INFO @ 23391368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_wfi_back_to_back 104941462443797216784223721673191583416947513132894927033242951654347152208799 113
UVM_INFO @ 17416831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_smoke 58537016725377067450645658626233415392351289960009576766007822198083792802895 107
UVM_INFO @ 144380056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* 1 test run
otbn_stress_all_with_rand_reset 107710050626814188199590460812240180638346922302333402777883426366259059470875 155
UVM_INFO @ 16760296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---