Simulation Results: otp_ctrl

 
15/09/2026 15:31:43 DVSim: v1.53.0 sha: 2e7b496 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 69.38 %
  • code
  • 69.54 %
  • assert
  • 93.05 %
  • func
  • 45.56 %
  • line
  • 86.88 %
  • branch
  • 83.51 %
  • cond
  • 85.18 %
  • toggle
  • 59.86 %
  • FSM
  • 32.28 %
Validation stages
V1
100.00%
V2
50.00%
V2S
55.56%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.830s 71.940us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 7.970s 331.961us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.120s 147.076us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 3.760s 670.476us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.890s 436.928us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.330s 97.153us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.990s 318.998us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 3.760s 670.476us 1 1 100.00
otp_ctrl_csr_aliasing 3.330s 97.153us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.250s 138.743us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.590s 545.097us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 152.610s 6995.996us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 5.620s 2771.523us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 6.950s 336.872us 0 1 0.00
otp_ctrl_check_fail 16.800s 3164.681us 0 1 0.00
regwen_during_otp_init 0 1 0.00
otp_ctrl_regwen 5.250s 116.166us 0 1 0.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 31.430s 1820.382us 0 1 0.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 8.300s 1012.776us 0 1 0.00
lc_interactions 1 2 50.00
otp_ctrl_parallel_lc_req 9.700s 1154.527us 1 1 100.00
otp_ctrl_parallel_lc_esc 4.460s 249.276us 0 1 0.00
otp_dai_errors 0 1 0.00
otp_ctrl_dai_errs 14.490s 2404.622us 0 1 0.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 16.590s 708.495us 1 1 100.00
test_access 0 1 0.00
otp_ctrl_test_access 8.630s 3237.923us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 71.640s 27141.317us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.380s 673.081us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.940s 1096.466us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 5.130s 1387.334us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 5.130s 1387.334us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.120s 147.076us 1 1 100.00
otp_ctrl_csr_rw 3.760s 670.476us 1 1 100.00
otp_ctrl_csr_aliasing 3.330s 97.153us 1 1 100.00
otp_ctrl_same_csr_outstanding 6.440s 711.512us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.120s 147.076us 1 1 100.00
otp_ctrl_csr_rw 3.760s 670.476us 1 1 100.00
otp_ctrl_csr_aliasing 3.330s 97.153us 1 1 100.00
otp_ctrl_same_csr_outstanding 6.440s 711.512us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 406.780s 16006.435us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 406.780s 16006.435us 1 1 100.00
otp_ctrl_tl_intg_err 20.790s 1677.687us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 406.780s 16006.435us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 406.780s 16006.435us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 20.790s 1677.687us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 7.970s 331.961us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 7.970s 331.961us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 406.780s 16006.435us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 406.780s 16006.435us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 406.780s 16006.435us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 406.780s 16006.435us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 406.780s 16006.435us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 406.780s 16006.435us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 406.780s 16006.435us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 406.780s 16006.435us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 406.780s 16006.435us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 406.780s 16006.435us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 406.780s 16006.435us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 406.780s 16006.435us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 406.780s 16006.435us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 406.780s 16006.435us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 406.780s 16006.435us 1 1 100.00
sec_cm_dai_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.460s 249.276us 0 1 0.00
otp_ctrl_sec_cm 406.780s 16006.435us 1 1 100.00
sec_cm_lci_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 4.460s 249.276us 0 1 0.00
sec_cm_kdi_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 4.460s 249.276us 0 1 0.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.460s 249.276us 0 1 0.00
otp_ctrl_macro_errs 16.590s 708.495us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 4.460s 249.276us 0 1 0.00
sec_cm_timer_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.460s 249.276us 0 1 0.00
otp_ctrl_sec_cm 406.780s 16006.435us 1 1 100.00
sec_cm_dai_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.460s 249.276us 0 1 0.00
otp_ctrl_sec_cm 406.780s 16006.435us 1 1 100.00
sec_cm_lci_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 4.460s 249.276us 0 1 0.00
sec_cm_kdi_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 4.460s 249.276us 0 1 0.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.460s 249.276us 0 1 0.00
otp_ctrl_macro_errs 16.590s 708.495us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 4.460s 249.276us 0 1 0.00
sec_cm_timer_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.460s 249.276us 0 1 0.00
otp_ctrl_sec_cm 406.780s 16006.435us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 5.620s 2771.523us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 16.800s 3164.681us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 31.430s 1820.382us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 31.430s 1820.382us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 31.430s 1820.382us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 31.430s 1820.382us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 31.430s 1820.382us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 7.970s 331.961us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 31.430s 1820.382us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 7.970s 331.961us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 406.780s 16006.435us 1 1 100.00
sec_cm_direct_access_config_regwen 0 1 0.00
otp_ctrl_regwen 5.250s 116.166us 0 1 0.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 7.970s 331.961us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 7.970s 331.961us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 16.590s 708.495us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 98.830s 26177.052us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 35.670s 1773.285us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 2 test runs
otp_ctrl_low_freq_read 15195849641478934893747353746846632168620902328665292895748037204481780713882 95
UVM_INFO @ 26177051898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 73607049093952442805270812268953305105943249845117745243538334658397151651791 96
UVM_INFO @ 27141316514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:419) scoreboard [scoreboard] Waited * cycles but did not see alert fatal_check_error. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 2 test runs
otp_ctrl_parallel_lc_esc 92281136048541902907010141305126320384670311724173576845354993940671707012887 1249
UVM_INFO @ 249275610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 42669716283421840615712391789102742867436202594377211480791985209525116903214 6684
UVM_INFO @ 2404621897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 2 test runs
otp_ctrl_parallel_key_req 41436813985958877032679187480299470014570013209320879852265838350839558614414 2900
UVM_INFO @ 1012775916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 60385618971099305207328148232700310965424395152421310120416868555746256613121 2952
UVM_INFO @ 3237923115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 22211723767106164839144381541111689993474118824259980664545799193163825687698 112881
UVM_INFO @ 6995995958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_background_chks 83230929897135008614951072031670447141917280032692558116021070518125118151785 2744
UVM_INFO @ 336871544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:674) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 1 test run
otp_ctrl_dai_lock 44973238475871984007077404888213358406929765610948213725672021493289467659948 20098
UVM_INFO @ 1820382488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_check_fail 73668700647335302992110251069269510352131343395118495223809356009481009829341 6560
UVM_INFO @ 3164680702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 1 test run
otp_ctrl_regwen 80204762802747499437664927980190013387477892253479083712368520846712559842976 4200
UVM_INFO @ 116165711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:786) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 672670554471348444612350501273034403442215422420150093769172676368619933140 7159
UVM_INFO @ 1773284781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---