Simulation Results: rom_ctrl/64kb

 
15/09/2026 15:31:43 DVSim: v1.53.0 sha: 2e7b496 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.48 %
  • code
  • 79.87 %
  • assert
  • 96.94 %
  • func
  • 97.62 %
  • block
  • 78.57 %
  • line
  • 79.10 %
  • branch
  • 79.53 %
  • toggle
  • 84.65 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
77.78%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.000s 395.127us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.000s 63.757us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.000s 70.286us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.000s 77.972us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 72.173us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.000s 136.795us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.000s 70.286us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 72.173us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.000s 79.167us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.000s 77.409us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.000s 12.925us 0 1 0.00
stress_all 0 1 0.00
rom_ctrl_stress_all 10800.000s 0.000us 0 1 0.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 5.000s 60.703us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.000s 78.534us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 3.000s 96.454us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 3.000s 96.454us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 63.757us 1 1 100.00
rom_ctrl_csr_rw 4.000s 70.286us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 72.173us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 73.306us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 63.757us 1 1 100.00
rom_ctrl_csr_rw 4.000s 70.286us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 72.173us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 73.306us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 5.000s 163.460us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 140.000s 245.652us 1 1 100.00
rom_ctrl_tl_intg_err 65.000s 446.229us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 140.000s 245.652us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 140.000s 245.652us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 140.000s 245.652us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 140.000s 245.652us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.000s 395.127us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.000s 395.127us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.000s 395.127us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 65.000s 446.229us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 5.000s 60.703us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 5.000s 163.460us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 140.000s 245.652us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 41.000s 2321.561us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
rom_ctrl_stress_all 44981378303780384057311933115886319357601024500373574139397367089360744588596 None
rom_ctrl_corrupt_sig_fatal_chk 1853228297887112774056714624010927428811902611127427035979737852563842077421 None
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 47178150122452640826320415029485213164983214933917264111345773509280195399750 88
UVM_INFO @ 12924777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---