Simulation Results: rstmgr

 
15/09/2026 15:31:43 DVSim: v1.53.0 sha: 2e7b496 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.94 %
  • code
  • 99.25 %
  • assert
  • 98.17 %
  • func
  • 96.39 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.75 %
  • toggle
  • 99.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.780s 70.855us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.760s 91.850us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.140s 36.016us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.800s 123.464us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.300s 36.913us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 2.560s 99.122us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.140s 36.016us 1 1 100.00
rstmgr_csr_aliasing 1.300s 36.913us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 2.120s 155.680us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.550s 47.516us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.280s 47.659us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 6.420s 501.284us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 6.420s 501.284us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 6.420s 501.284us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 6.420s 501.284us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 18.060s 2477.455us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 2.110s 104.188us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 3.260s 51.068us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 3.260s 51.068us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.760s 91.850us 1 1 100.00
rstmgr_csr_rw 1.140s 36.016us 1 1 100.00
rstmgr_csr_aliasing 1.300s 36.913us 1 1 100.00
rstmgr_same_csr_outstanding 1.420s 41.291us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.760s 91.850us 1 1 100.00
rstmgr_csr_rw 1.140s 36.016us 1 1 100.00
rstmgr_csr_aliasing 1.300s 36.913us 1 1 100.00
rstmgr_same_csr_outstanding 1.420s 41.291us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 52.480s 6742.058us 1 1 100.00
rstmgr_tl_intg_err 4.540s 617.193us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 52.480s 6742.058us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 52.480s 6742.058us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 4.540s 617.193us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.590s 65.508us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.310s 464.743us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 3.410s 293.724us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 52.480s 6742.058us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.140s 36.016us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.140s 36.016us 1 1 100.00