Simulation Results

Simulation Results: rv_dm/use_dmi_interface

15/09/2026 15:31:43 DVSim: v1.53.0 sha: 2e7b496 json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
87.13 %

code
74.10 %

assert
96.66 %

func
90.62 %

block
89.80 %

line
89.78 %

branch
72.32 %

toggle
71.80 %

FSM
62.50 %

Validation stages

V1		92.59%
V2		69.57%
V2S		100.00%
V3		0.00%
unmapped		0.00%

25/27 passed

92.59 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	55.000s	1422.396us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	47.000s	515.536us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	44.000s	129.150us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	35.000s	8920.473us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	46.000s	723.497us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	59.000s	3183.416us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	55.000s	5240.800us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	69.000s	15498.111us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	59.000s	5914.435us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	46.000s	769.235us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	44.000s	449.176us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	49.000s	765.068us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	50.000s	400.763us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	43.000s	183.377us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	50.000s	1374.193us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	47.000s	295.417us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	52.000s	736.679us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	46.000s	769.235us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	51.000s	586.256us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	46.000s	234.680us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	49.000s	765.068us	1	1	100.00
rom_read_access				0	1	0.00
	rv_dm_rom_read_access	44.000s	74.901us	0	1	0.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	49.000s	611.670us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	47.000s	149.298us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	84.000s	20941.282us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	41.000s	2421.258us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	50.000s	251.616us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	41.000s	2421.258us	1	1	100.00
	rv_dm_csr_rw	47.000s	149.298us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	37.000s	43.215us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	36.000s	90.190us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	55.000s	1422.396us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	40.000s	286.742us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	51.000s	484.949us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	45.000s	324.380us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	54.000s	1081.281us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	47.000s	1886.531us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	48.000s	146.158us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	57.000s	3293.359us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	146.000s	101370.824us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	43.000s	181.252us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	52.000s	2145.587us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	52.000s	729.122us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	46.000s	223.898us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	50.000s	4829.321us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	76.000s	3221.470us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	51.000s	156.468us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	47.000s	1932.595us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	51.000s	69.623us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	42.000s	581.400us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	42.000s	581.400us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	41.000s	2421.258us	1	1	100.00
	rv_dm_csr_hw_reset	49.000s	611.670us	1	1	100.00
	rv_dm_csr_rw	47.000s	149.298us	1	1	100.00
	rv_dm_same_csr_outstanding	48.000s	2073.177us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	41.000s	2421.258us	1	1	100.00
	rv_dm_csr_hw_reset	49.000s	611.670us	1	1	100.00
	rv_dm_csr_rw	47.000s	149.298us	1	1	100.00
	rv_dm_same_csr_outstanding	48.000s	2073.177us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	43.000s	2922.769us	1	1	100.00
	rv_dm_tl_intg_err	65.000s	6259.897us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	65.000s	6259.897us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	52.000s	2145.587us	1	1	100.00
	rv_dm_debug_disabled	45.000s	88.734us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	52.000s	2145.587us	1	1	100.00
	rv_dm_debug_disabled	45.000s	88.734us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	55.000s	1422.396us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	48.000s	235.269us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	48.000s	97.636us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	48.000s	97.636us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	48.000s	235.269us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	49.000s	403.966us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	424.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:481) [scoreboard] sba_tl_access_q item uncompared:				3 test runs
	rv_dm_sba_tl_access	76926855812233489732947071158159956445014383156043507887064744919326251904558	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23836
	rv_dm_bad_sba_tl_access	55682994382948971766377132869981952644866307718089353917067512655197071351160	114	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24409
	rv_dm_autoincr_sba_tl_access	101437236539351925847053481970546944997772118989969346044523279931585798368688	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23922
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				2 test runs
	rv_dm_jtag_dmi_debug_disabled	19563799668935940520993084171534864850381703675991461397662149712016482824027	87	UVM_INFO @ 181252066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	57222196773711395712813547791376691879144935884912690400555533016705666033726	89	UVM_INFO @ 1932594918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				1 test run
	rv_dm_delayed_resp_sba_tl_access	57781882597423449866493709095640605890760655130015356358488035775226639136397	107	UVM_INFO @ 146157626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				1 test run
	rv_dm_mem_tl_access_resuming	8503027332693453245473760875911808030110044687353807244051622376388023057948	87	UVM_INFO @ 400762813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				1 test run
	rv_dm_hart_unavail	46335075236585956917554589063857659432275987521695346125786629944516314279527	87	UVM_INFO @ 223898174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=, but it was "}. Item: (req: (cip_tl_seq_item@23890) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }				1 test run
	rv_dm_rom_read_access	41635466920880775974822005490267059303771872622039023804749084130750198131637	87	). UVM_INFO @ 74901409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	108101749998917438210813042075389995739304028592646890892176657677975074494516	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1230) [rv_dm_common_vseq] Check failed (vseq_done)				1 test run
	rv_dm_stress_all_with_rand_reset	95136218030403027435059514177864911795978132539258093660492783508926678015423	95	UVM_INFO @ 403965987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---