Simulation Results: rv_timer

 
15/09/2026 15:31:43 DVSim: v1.53.0 sha: 2e7b496 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 95.66 %
  • code
  • 90.45 %
  • assert
  • 96.52 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.000s 186.806us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 18.607us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 39.342us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 4.000s 613.040us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 2.000s 13.454us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 53.079us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 39.342us 1 1 100.00
rv_timer_csr_aliasing 2.000s 13.454us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 3.000s 1144.992us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 793.668us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 88.000s 55854.088us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 88.000s 55854.088us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 10.000s 505.795us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 2.000s 17.265us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 14.231us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 37.481us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 37.481us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 18.607us 1 1 100.00
rv_timer_csr_rw 1.000s 39.342us 1 1 100.00
rv_timer_csr_aliasing 2.000s 13.454us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 124.650us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 18.607us 1 1 100.00
rv_timer_csr_rw 1.000s 39.342us 1 1 100.00
rv_timer_csr_aliasing 2.000s 13.454us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 124.650us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 118.277us 1 1 100.00
rv_timer_tl_intg_err 1.000s 113.533us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.000s 113.533us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.000s 246.166us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 1.000s 85.548us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 57.000s 16220.587us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:183) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 15927107449080924926945156670436018980368750310078928149120239024670118243279 86
UVM_INFO @ 246165848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 11940355804071578109039098999485252344090650579930593002816531975278594486954 84
UVM_INFO @ 85548209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---