Simulation Results: spi_host

 
15/09/2026 15:31:43 DVSim: v1.53.0 sha: 2e7b496 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.82 %
  • code
  • 91.30 %
  • assert
  • 95.09 %
  • func
  • 89.08 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 26.000s 4543.693us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 18.859us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 18.031us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 4.000s 955.539us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 15.712us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 28.046us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 18.031us 1 1 100.00
spi_host_csr_aliasing 1.000s 15.712us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 15.426us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 63.082us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 32.387us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 321.432us 1 1 100.00
spi_host_error_cmd 1.000s 16.551us 1 1 100.00
spi_host_event 14.000s 1545.546us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 111.179us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 111.179us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 111.179us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 208.000s 17696.328us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 4.000s 126.535us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 247.024us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 111.179us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 111.179us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 26.000s 4543.693us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 26.000s 4543.693us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 4.000s 276.724us 1 1 100.00
spien 1 1 100.00
spi_host_spien 2.000s 215.731us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 314.000s 103298.673us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 3.000s 350.258us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 321.432us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 44.234us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 42.121us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 140.228us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 140.228us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 18.859us 1 1 100.00
spi_host_csr_rw 2.000s 18.031us 1 1 100.00
spi_host_csr_aliasing 1.000s 15.712us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 20.489us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 18.859us 1 1 100.00
spi_host_csr_rw 2.000s 18.031us 1 1 100.00
spi_host_csr_aliasing 1.000s 15.712us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 20.489us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 77.623us 1 1 100.00
spi_host_sec_cm 2.000s 69.064us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 77.623us 1 1 100.00