Simulation Results: sram_ctrl/main

 
15/09/2026 15:31:43 DVSim: v1.53.0 sha: 2e7b496 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 95.14 %
  • code
  • 94.32 %
  • assert
  • 97.69 %
  • func
  • 93.40 %
  • block
  • 93.47 %
  • line
  • 94.53 %
  • branch
  • 90.91 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 1311.928us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 39.408us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 21.859us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 383.290us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 34.686us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 683.877us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 21.859us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 34.686us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 194.000s 65280.851us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 49.000s 1888.430us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 50.000s 26918.973us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 231.000s 13410.926us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 212.000s 15782.789us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 26.000s 5008.663us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 7.000s 4781.193us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 12.000s 1695.673us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 1887.120us 1 1 100.00
sram_ctrl_partial_access_b2b 184.000s 13266.509us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 7.000s 2787.556us 1 1 100.00
sram_ctrl_throughput_w_partial_write 5.000s 829.347us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 682.028us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 18.000s 13741.762us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 884.623us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 4.000s 1311.928us 1 1 100.00
sram_ctrl_partial_access 4.000s 1887.120us 1 1 100.00
sram_ctrl_access_during_key_req 26.000s 5008.663us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 514.000s 51515.615us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 14.610us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 6.000s 298.592us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 6.000s 298.592us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 39.408us 1 1 100.00
sram_ctrl_csr_rw 1.000s 21.859us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 34.686us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 13.760us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 39.408us 1 1 100.00
sram_ctrl_csr_rw 1.000s 21.859us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 34.686us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 13.760us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 22.000s 11197.507us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 1899.447us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 201.526us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 1899.447us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 201.526us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 18.000s 13741.762us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 18.000s 13741.762us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 21.859us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 12.000s 1695.673us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 1695.673us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 1695.673us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 7.000s 4781.193us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 22.000s 11197.507us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 1311.928us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 1311.928us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 12.000s 1695.673us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 1899.447us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 7.000s 4781.193us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 1899.447us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1899.447us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 1311.928us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1899.447us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 28.000s 1043.993us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 14144445612305915217870626268850680039108685095080653933322378813911017486248 None
sram_ctrl_mubi_enc_err 5135314761909323401614511615000518107378493645463906605561413615080799631969 None