Simulation Results: sram_ctrl/ret

 
15/09/2026 15:31:43 DVSim: v1.53.0 sha: 2e7b496 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.46 %
  • code
  • 81.50 %
  • assert
  • 98.08 %
  • func
  • 94.80 %
  • block
  • 91.85 %
  • line
  • 93.41 %
  • branch
  • 87.60 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 62.487us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 19.439us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 15.903us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 35.556us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 11.801us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 29.831us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 15.903us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 11.801us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 9.000s 1627.959us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 63.569us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 13.000s 861.590us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 262.000s 15435.630us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 9.000s 489.603us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 7.000s 949.110us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 7.000s 1342.183us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 12.000s 1504.591us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 83.885us 1 1 100.00
sram_ctrl_partial_access_b2b 397.000s 199339.727us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 1.000s 42.235us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 149.023us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 40.302us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 15.000s 3358.117us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 82.866us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 2.000s 62.487us 1 1 100.00
sram_ctrl_partial_access 2.000s 83.885us 1 1 100.00
sram_ctrl_access_during_key_req 7.000s 949.110us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 52.000s 13253.167us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 20.851us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 93.456us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 93.456us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 19.439us 1 1 100.00
sram_ctrl_csr_rw 2.000s 15.903us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 11.801us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 56.754us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 19.439us 1 1 100.00
sram_ctrl_csr_rw 2.000s 15.903us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 11.801us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 56.754us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 1242.830us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 225.513us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 917.144us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 225.513us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 917.144us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 15.000s 3358.117us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 15.000s 3358.117us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 15.903us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 12.000s 1504.591us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 1504.591us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 1504.591us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 7.000s 1342.183us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3601.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 1242.830us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 62.487us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 62.487us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 12.000s 1504.591us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 225.513us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 7.000s 1342.183us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 225.513us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 225.513us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 62.487us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 225.513us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 30.000s 663.270us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 103222953375700087183146272029560002245998315086896529977066796258889789569896 None
sram_ctrl_mubi_enc_err 49733212450596921829933347153861909664205457759737905947223707908351113097884 None