Simulation Results: uart

 
15/09/2026 15:31:43 DVSim: v1.53.0 sha: 2e7b496 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 93.35 %
  • code
  • 92.73 %
  • assert
  • 97.12 %
  • func
  • 90.20 %
  • block
  • 99.08 %
  • line
  • 99.52 %
  • branch
  • 98.34 %
  • toggle
  • 73.08 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 3.000s 292.639us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 37.828us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 34.709us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 3.000s 523.249us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 2.000s 19.896us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 2.000s 48.176us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 34.709us 1 1 100.00
uart_csr_aliasing 2.000s 19.896us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 45.000s 71066.300us 1 1 100.00
parity 2 2 100.00
uart_smoke 3.000s 292.639us 1 1 100.00
uart_tx_rx 45.000s 71066.300us 1 1 100.00
parity_error 2 2 100.00
uart_intr 13.000s 25257.048us 1 1 100.00
uart_rx_parity_err 130.000s 145814.155us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 45.000s 71066.300us 1 1 100.00
uart_intr 13.000s 25257.048us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 34.000s 87840.976us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 25.000s 60920.297us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 75.000s 45262.756us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 13.000s 25257.048us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 13.000s 25257.048us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 13.000s 25257.048us 1 1 100.00
perf 1 1 100.00
uart_perf 120.000s 42231.165us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.000s 353.223us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.000s 353.223us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 24.000s 21570.985us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.000s 583.188us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.000s 1231.611us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 4.000s 2451.150us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 255.000s 237677.919us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 450.000s 267045.695us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 2.000s 36.623us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 14.106us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 86.191us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 86.191us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 37.828us 1 1 100.00
uart_csr_rw 1.000s 34.709us 1 1 100.00
uart_csr_aliasing 2.000s 19.896us 1 1 100.00
uart_same_csr_outstanding 2.000s 18.893us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 37.828us 1 1 100.00
uart_csr_rw 1.000s 34.709us 1 1 100.00
uart_csr_aliasing 2.000s 19.896us 1 1 100.00
uart_same_csr_outstanding 2.000s 18.893us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 149.268us 1 1 100.00
uart_tl_intg_err 2.000s 345.720us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 2.000s 345.720us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 11.000s 9412.622us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty 1 test run
uart_stress_all 62444776740922315885755218473098622171897164619539506399464404093783031127193 96
UVM_INFO @ 117817095277 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/9
UVM_INFO @ 120834415277 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 5/9
UVM_INFO @ 123354007466 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 6/9
UVM_INFO @ 123579455277 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 7/9