Simulation Results: ac_range_check

 
16/09/2026 15:31:42 DVSim: v1.53.0 sha: aecc39b json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 82.89 %
  • code
  • 93.00 %
  • assert
  • 97.75 %
  • func
  • 57.93 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 80.82 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 35.000s 1547.237us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 37.000s 688.773us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 10.000s 52.984us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 9.000s 34.003us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 42.000s 730.002us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 11.000s 74.041us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 10.000s 40.100us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 9.000s 34.003us 1 1 100.00
ac_range_check_csr_aliasing 11.000s 74.041us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 11.000s 431.796us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 46.000s 13482.200us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 317.000s 49578.988us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 9.000s 47.384us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 9.000s 23.660us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 4.000s 155.150us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 4.000s 155.150us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 10.000s 52.984us 1 1 100.00
ac_range_check_csr_rw 9.000s 34.003us 1 1 100.00
ac_range_check_csr_aliasing 11.000s 74.041us 1 1 100.00
ac_range_check_same_csr_outstanding 10.000s 56.852us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 10.000s 52.984us 1 1 100.00
ac_range_check_csr_rw 9.000s 34.003us 1 1 100.00
ac_range_check_csr_aliasing 11.000s 74.041us 1 1 100.00
ac_range_check_same_csr_outstanding 10.000s 56.852us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 21.000s 4220.914us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 21.000s 4220.914us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 21.000s 4220.914us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 21.000s 4220.914us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 72.000s 8472.282us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 5.000s 22.341us 1 1 100.00
ac_range_check_tl_intg_err 9.000s 709.053us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 270.000s 2145.005us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 32.000s 11542.251us 1 1 100.00