Simulation Results: aes/gcm_masked

 
16/09/2026 15:31:42 DVSim: v1.53.0 sha: aecc39b json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 86.69 %
  • code
  • 95.12 %
  • assert
  • 98.29 %
  • func
  • 66.67 %
  • block
  • 95.73 %
  • line
  • 97.44 %
  • branch
  • 89.50 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
94.74%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 118.690us 1 1 100.00
smoke 1 1 100.00
aes_smoke 5.000s 303.382us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 58.080us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 82.829us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 196.985us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 67.965us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 110.899us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 82.829us 1 1 100.00
aes_csr_aliasing 2.000s 67.965us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 5.000s 303.382us 1 1 100.00
aes_config_error 4.000s 104.621us 1 1 100.00
aes_stress 5.000s 118.899us 1 1 100.00
key_length 3 3 100.00
aes_smoke 5.000s 303.382us 1 1 100.00
aes_config_error 4.000s 104.621us 1 1 100.00
aes_stress 5.000s 118.899us 1 1 100.00
back2back 2 2 100.00
aes_stress 5.000s 118.899us 1 1 100.00
aes_b2b 14.000s 217.971us 1 1 100.00
backpressure 1 1 100.00
aes_stress 5.000s 118.899us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 5.000s 303.382us 1 1 100.00
aes_config_error 4.000s 104.621us 1 1 100.00
aes_stress 5.000s 118.899us 1 1 100.00
aes_alert_reset 3.000s 110.559us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 55.400us 1 1 100.00
aes_config_error 4.000s 104.621us 1 1 100.00
aes_alert_reset 3.000s 110.559us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 7.000s 365.673us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 36.000s 2572.195us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 13.000s 298.433us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 110.559us 1 1 100.00
stress 1 1 100.00
aes_stress 5.000s 118.899us 1 1 100.00
sideload 2 2 100.00
aes_stress 5.000s 118.899us 1 1 100.00
aes_sideload 4.000s 86.896us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 4.000s 625.356us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 8.000s 156.026us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 98.730us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 74.036us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 4.000s 553.560us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 4.000s 553.560us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 58.080us 1 1 100.00
aes_csr_rw 2.000s 82.829us 1 1 100.00
aes_csr_aliasing 2.000s 67.965us 1 1 100.00
aes_same_csr_outstanding 3.000s 121.906us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 58.080us 1 1 100.00
aes_csr_rw 2.000s 82.829us 1 1 100.00
aes_csr_aliasing 2.000s 67.965us 1 1 100.00
aes_same_csr_outstanding 3.000s 121.906us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 150.447us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 6.000s 388.211us 0 1 0.00
aes_control_fi 2.000s 51.713us 1 1 100.00
aes_cipher_fi 3.000s 53.475us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 90.525us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 90.525us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 90.525us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 90.525us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 826.328us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 11.000s 1178.314us 1 1 100.00
aes_tl_intg_err 3.000s 100.142us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 100.142us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 110.559us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 90.525us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 90.525us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 5.000s 303.382us 1 1 100.00
aes_stress 5.000s 118.899us 1 1 100.00
aes_alert_reset 3.000s 110.559us 1 1 100.00
aes_core_fi 65.000s 10013.769us 0 1 0.00
sec_cm_gcm_config_sparse 3 4 75.00
aes_gcm_save_restore 3.000s 98.730us 1 1 100.00
aes_config_error 4.000s 104.621us 1 1 100.00
aes_stress 5.000s 118.899us 1 1 100.00
aes_core_fi 65.000s 10013.769us 0 1 0.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 90.525us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 108.568us 1 1 100.00
aes_stress 5.000s 118.899us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 5.000s 118.899us 1 1 100.00
aes_sideload 4.000s 86.896us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 108.568us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 108.568us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 108.568us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 108.568us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 108.568us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 5.000s 118.899us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 5.000s 118.899us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 6.000s 388.211us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 6.000s 388.211us 0 1 0.00
aes_control_fi 2.000s 51.713us 1 1 100.00
aes_cipher_fi 3.000s 53.475us 1 1 100.00
aes_ctr_fi 2.000s 49.679us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 6.000s 388.211us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 6.000s 388.211us 0 1 0.00
aes_control_fi 2.000s 51.713us 1 1 100.00
aes_cipher_fi 3.000s 53.475us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 53.475us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 6.000s 388.211us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 6.000s 388.211us 0 1 0.00
aes_control_fi 2.000s 51.713us 1 1 100.00
aes_ctr_fi 2.000s 49.679us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 6.000s 388.211us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 6.000s 388.211us 0 1 0.00
aes_control_fi 2.000s 51.713us 1 1 100.00
aes_cipher_fi 3.000s 53.475us 1 1 100.00
aes_ctr_fi 2.000s 49.679us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 110.559us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 6.000s 388.211us 0 1 0.00
aes_control_fi 2.000s 51.713us 1 1 100.00
aes_cipher_fi 3.000s 53.475us 1 1 100.00
aes_ctr_fi 2.000s 49.679us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 6.000s 388.211us 0 1 0.00
aes_control_fi 2.000s 51.713us 1 1 100.00
aes_cipher_fi 3.000s 53.475us 1 1 100.00
aes_ctr_fi 2.000s 49.679us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 6.000s 388.211us 0 1 0.00
aes_control_fi 2.000s 51.713us 1 1 100.00
aes_ctr_fi 2.000s 49.679us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_ghash_fi 2.000s 328.416us 1 1 100.00
aes_fi 6.000s 388.211us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 6.000s 388.211us 0 1 0.00
aes_control_fi 2.000s 51.713us 1 1 100.00
aes_cipher_fi 3.000s 53.475us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 26.000s 2955.541us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_stress_all 45917042796421354949880934124009431883053011350007636173702854870784294432984 23942
UVM_INFO @ 156025901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 44678572559653791768383314062978497707932910931243704223185999437908743559316 416
UVM_INFO @ 2955541278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 40766498288783941526275082230313355873290809495764255785394792685869157907889 6253
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 4
----| Expected corrupted: 0
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 1 test run
aes_core_fi 76800871672474931469599982107660116997523863687230953974868542101353629521332 150
UVM_INFO @ 10013769480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---