Simulation Results: aes/gcm_unmasked

 
16/09/2026 15:31:42 DVSim: v1.53.0 sha: aecc39b json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 83.83 %
  • code
  • 90.78 %
  • assert
  • 97.75 %
  • func
  • 62.96 %
  • block
  • 90.15 %
  • line
  • 92.11 %
  • branch
  • 82.25 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 100.026us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 178.667us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 80.448us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 56.190us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 7.000s 1802.429us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 83.931us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 152.012us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 56.190us 1 1 100.00
aes_csr_aliasing 2.000s 83.931us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 178.667us 1 1 100.00
aes_config_error 4.000s 333.876us 1 1 100.00
aes_stress 3.000s 140.827us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 178.667us 1 1 100.00
aes_config_error 4.000s 333.876us 1 1 100.00
aes_stress 3.000s 140.827us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 140.827us 1 1 100.00
aes_b2b 5.000s 113.349us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 140.827us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 178.667us 1 1 100.00
aes_config_error 4.000s 333.876us 1 1 100.00
aes_stress 3.000s 140.827us 1 1 100.00
aes_alert_reset 3.000s 119.529us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 72.080us 1 1 100.00
aes_config_error 4.000s 333.876us 1 1 100.00
aes_alert_reset 3.000s 119.529us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 219.279us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 921.815us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 119.529us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 140.827us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 140.827us 1 1 100.00
aes_sideload 3.000s 82.799us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 82.420us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 4.000s 389.412us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 82.658us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 152.081us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 152.081us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 80.448us 1 1 100.00
aes_csr_rw 2.000s 56.190us 1 1 100.00
aes_csr_aliasing 2.000s 83.931us 1 1 100.00
aes_same_csr_outstanding 2.000s 70.854us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 80.448us 1 1 100.00
aes_csr_rw 2.000s 56.190us 1 1 100.00
aes_csr_aliasing 2.000s 83.931us 1 1 100.00
aes_same_csr_outstanding 2.000s 70.854us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 132.626us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 4.000s 371.825us 0 1 0.00
aes_control_fi 2.000s 100.376us 1 1 100.00
aes_cipher_fi 3.000s 51.966us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 138.245us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 138.245us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 138.245us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 138.245us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 124.359us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 887.714us 1 1 100.00
aes_tl_intg_err 2.000s 127.738us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 127.738us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 119.529us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 138.245us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 138.245us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 178.667us 1 1 100.00
aes_stress 3.000s 140.827us 1 1 100.00
aes_alert_reset 3.000s 119.529us 1 1 100.00
aes_core_fi 2.000s 60.788us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 4.000s 333.876us 1 1 100.00
aes_stress 3.000s 140.827us 1 1 100.00
aes_core_fi 2.000s 60.788us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 138.245us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 79.029us 1 1 100.00
aes_stress 3.000s 140.827us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 140.827us 1 1 100.00
aes_sideload 3.000s 82.799us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 79.029us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 79.029us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 79.029us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 79.029us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 79.029us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 140.827us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 140.827us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 4.000s 371.825us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 4.000s 371.825us 0 1 0.00
aes_control_fi 2.000s 100.376us 1 1 100.00
aes_cipher_fi 3.000s 51.966us 1 1 100.00
aes_ctr_fi 2.000s 57.894us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 4.000s 371.825us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 4.000s 371.825us 0 1 0.00
aes_control_fi 2.000s 100.376us 1 1 100.00
aes_cipher_fi 3.000s 51.966us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 51.966us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 4.000s 371.825us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 4.000s 371.825us 0 1 0.00
aes_control_fi 2.000s 100.376us 1 1 100.00
aes_ctr_fi 2.000s 57.894us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 4.000s 371.825us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 4.000s 371.825us 0 1 0.00
aes_control_fi 2.000s 100.376us 1 1 100.00
aes_cipher_fi 3.000s 51.966us 1 1 100.00
aes_ctr_fi 2.000s 57.894us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 119.529us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 4.000s 371.825us 0 1 0.00
aes_control_fi 2.000s 100.376us 1 1 100.00
aes_cipher_fi 3.000s 51.966us 1 1 100.00
aes_ctr_fi 2.000s 57.894us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 4.000s 371.825us 0 1 0.00
aes_control_fi 2.000s 100.376us 1 1 100.00
aes_cipher_fi 3.000s 51.966us 1 1 100.00
aes_ctr_fi 2.000s 57.894us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 4.000s 371.825us 0 1 0.00
aes_control_fi 2.000s 100.376us 1 1 100.00
aes_ctr_fi 2.000s 57.894us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 4.000s 371.825us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 4.000s 371.825us 0 1 0.00
aes_control_fi 2.000s 100.376us 1 1 100.00
aes_cipher_fi 3.000s 51.966us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 14.174us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 89919713953916972267178455988657119653426286037201212942064372595115057258067 4143
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 71992185235667265608920026613006541602538345875640034696150572030823433680183 174
UVM_INFO @ 14174289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---