Simulation Results: clkmgr

 
16/09/2026 15:31:42 DVSim: v1.53.0 sha: aecc39b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.73 %
  • code
  • 69.83 %
  • assert
  • 89.88 %
  • func
  • 67.48 %
  • line
  • 82.32 %
  • branch
  • 87.53 %
  • cond
  • 79.28 %
  • toggle
  • 100.00 %
  • FSM
  • 0.00 %
Validation stages
V1
83.33%
V2
69.23%
V2S
50.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.670s 45.879us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.850s 15.361us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.130s 13.613us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 2.430s 63.452us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.770s 56.386us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.450s 24.277us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 1.130s 13.613us 1 1 100.00
clkmgr_csr_aliasing 1.770s 56.386us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.790s 13.226us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.250s 19.771us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.070s 24.261us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.670s 45.879us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 1.800s 94.148us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.960s 7.040us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 1.800s 94.148us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 2.170s 117.285us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.170s 18.613us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 9.430s 567.178us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 9.430s 567.178us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
clkmgr_csr_hw_reset 0.850s 15.361us 1 1 100.00
clkmgr_csr_rw 1.130s 13.613us 1 1 100.00
clkmgr_csr_aliasing 1.770s 56.386us 1 1 100.00
clkmgr_same_csr_outstanding 1.000s 7.029us 0 1 0.00
tl_d_partial_access 3 4 75.00
clkmgr_csr_hw_reset 0.850s 15.361us 1 1 100.00
clkmgr_csr_rw 1.130s 13.613us 1 1 100.00
clkmgr_csr_aliasing 1.770s 56.386us 1 1 100.00
clkmgr_same_csr_outstanding 1.000s 7.029us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 2.680s 161.291us 1 1 100.00
clkmgr_tl_intg_err 0.920s 2.215us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 2.660s 165.615us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 2.660s 165.615us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 2.660s 165.615us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 2.660s 165.615us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.900s 2.946us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.920s 2.215us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 1.800s 94.148us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.960s 7.040us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 2.660s 165.615us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.300s 19.704us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.130s 13.613us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 2.680s 161.291us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.130s 13.613us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.130s 13.613us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 2.680s 161.291us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.920s 5.479us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 0.900s 4.296us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 42150407995336093073318980629879216731470781274000903537103951431637182368871 84
UVM_INFO @ 94147518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 106561186443889160653907057228883327383769177929633740589935455949225769583049 161
UVM_INFO @ 117284800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 106495008658252526839189136773589063331839204478791334810320923037917818111248 84
UVM_INFO @ 7040449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 70195657090590919234973812769962340191936060350882552922487909919930784278027 85
UVM_INFO @ 4295508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 30913152981696890630791366785915408473987746203628562816737775246250409927709 80
UVM_INFO @ 5479252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 31937612379267568592536866146574954409517077792434541146621272093200223488350 81
UVM_INFO @ 2946336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 1 test run
clkmgr_tl_intg_err 99001015919777560193881501752811516459779194822293510170165494172255289646439 88
UVM_INFO @ 2215317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 87695075471795490681382261152141667024765328430607377282796780269390637740798 81
UVM_INFO @ 63452086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 107048106512419541672439708982974603058770176648887586684306352531025832408494 81
UVM_INFO @ 7029265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---