Simulation Results: csrng

 
16/09/2026 15:31:42 DVSim: v1.53.0 sha: aecc39b json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.30 %
  • code
  • 92.17 %
  • assert
  • 94.54 %
  • func
  • 78.17 %
  • block
  • 96.80 %
  • line
  • 97.63 %
  • branch
  • 92.05 %
  • toggle
  • 93.31 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 29.031us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 3.000s 68.189us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 1.000s 21.923us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 14.000s 611.985us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 4.000s 87.724us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 4.000s 106.649us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 1.000s 21.923us 1 1 100.00
csrng_csr_aliasing 4.000s 87.724us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 189.386us 1 1 100.00
alerts 1 1 100.00
csrng_alert 10.000s 343.207us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 21.872us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 37.000s 2325.372us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 37.000s 2325.372us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 4.000s 113.987us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 20.760us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 17.834us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 3.000s 60.912us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 3.000s 60.912us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 3.000s 68.189us 1 1 100.00
csrng_csr_rw 1.000s 21.923us 1 1 100.00
csrng_csr_aliasing 4.000s 87.724us 1 1 100.00
csrng_same_csr_outstanding 2.000s 32.928us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 3.000s 68.189us 1 1 100.00
csrng_csr_rw 1.000s 21.923us 1 1 100.00
csrng_csr_aliasing 4.000s 87.724us 1 1 100.00
csrng_same_csr_outstanding 2.000s 32.928us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 4.000s 125.582us 1 1 100.00
csrng_tl_intg_err 3.000s 94.362us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 25.011us 1 1 100.00
csrng_csr_rw 1.000s 21.923us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 10.000s 343.207us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 4.000s 113.987us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 189.386us 1 1 100.00
csrng_err 2.000s 21.872us 1 1 100.00
csrng_sec_cm 4.000s 125.582us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 189.386us 1 1 100.00
csrng_err 2.000s 21.872us 1 1 100.00
csrng_sec_cm 4.000s 125.582us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 189.386us 1 1 100.00
csrng_err 2.000s 21.872us 1 1 100.00
csrng_sec_cm 4.000s 125.582us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 189.386us 1 1 100.00
csrng_err 2.000s 21.872us 1 1 100.00
csrng_sec_cm 4.000s 125.582us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 189.386us 1 1 100.00
csrng_err 2.000s 21.872us 1 1 100.00
csrng_sec_cm 4.000s 125.582us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 10.000s 343.207us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 189.386us 1 1 100.00
csrng_err 2.000s 21.872us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 4.000s 113.987us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 10.000s 343.207us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 3.000s 94.362us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 189.386us 1 1 100.00
csrng_err 2.000s 21.872us 1 1 100.00
csrng_sec_cm 4.000s 125.582us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 189.386us 1 1 100.00
csrng_err 2.000s 21.872us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 189.386us 1 1 100.00
csrng_err 2.000s 21.872us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 189.386us 1 1 100.00
csrng_err 2.000s 21.872us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 189.386us 1 1 100.00
csrng_err 2.000s 21.872us 1 1 100.00
csrng_sec_cm 4.000s 125.582us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 189.386us 1 1 100.00
csrng_err 2.000s 21.872us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3.000s 9.109us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:1230) [csrng_common_vseq] Check failed (vseq_done) 1 test run
csrng_stress_all_with_rand_reset 47933738222783957662238360001686838153387100549228175653327534398053902897239 116
UVM_INFO @ 9109066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---