Simulation Results: dma

 
16/09/2026 15:31:42 DVSim: v1.53.0 sha: aecc39b json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 83.24 %
  • code
  • 90.41 %
  • assert
  • 96.40 %
  • func
  • 62.91 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 77.37 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 6.000s 2364.422us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 241.154us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 280.818us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 17.635us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 17.528us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 17.000s 6407.994us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 2.000s 141.527us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 21.378us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 17.528us 1 1 100.00
dma_csr_aliasing 2.000s 141.527us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 61.000s 15459.910us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 578.000s 141495.312us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 248.000s 17015.998us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 248.000s 17015.998us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 578.000s 141495.312us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 723.000s 84280.848us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 248.000s 17015.998us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 12.000s 11614.435us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 157.000s 9727.435us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 13.503us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 2.000s 50.038us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 117.518us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 117.518us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 17.635us 1 1 100.00
dma_csr_rw 2.000s 17.528us 1 1 100.00
dma_csr_aliasing 2.000s 141.527us 1 1 100.00
dma_same_csr_outstanding 2.000s 52.547us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 17.635us 1 1 100.00
dma_csr_rw 2.000s 17.528us 1 1 100.00
dma_csr_aliasing 2.000s 141.527us 1 1 100.00
dma_same_csr_outstanding 2.000s 52.547us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 13.000s 247.034us 1 1 100.00
dma_generic_stress 723.000s 84280.848us 1 1 100.00
dma_handshake_stress 248.000s 17015.998us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 7.000s 1438.168us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 2.000s 97.441us 1 1 100.00
dma_sec_cm 2.000s 38.069us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 143.000s 17430.475us 1 1 100.00
dma_longer_transfer 8.000s 287.781us 1 1 100.00
dma_stress_all_with_rand_reset 23.000s 3479.858us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1297) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 43474446658597605585192235135847498632994061603908417489923801063672074544697 120
UVM_INFO @ 3479858201ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---