Simulation Results: edn/edn0

 
16/09/2026 15:31:42 DVSim: v1.53.0 sha: aecc39b json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 75.95 %
  • code
  • 82.61 %
  • assert
  • 94.91 %
  • func
  • 50.35 %
  • block
  • 93.82 %
  • line
  • 96.78 %
  • branch
  • 86.75 %
  • toggle
  • 67.05 %
  • FSM
  • 79.84 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 28.315us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 18.291us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 22.010us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.000s 661.165us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.000s 40.225us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 71.686us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 22.010us 1 1 100.00
edn_csr_aliasing 1.000s 40.225us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 80.145us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 80.145us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 80.145us 1 1 100.00
interrupts 1 1 100.00
edn_intr 2.000s 21.092us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 39.529us 1 1 100.00
errs 1 1 100.00
edn_err 3.000s 187.395us 1 1 100.00
disable 2 2 100.00
edn_disable 2.000s 42.015us 1 1 100.00
edn_disable_auto_req_mode 4.000s 44.683us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 10.000s 121.658us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 2.000s 92.713us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 2.000s 68.314us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.000s 110.237us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.000s 110.237us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 2.000s 18.291us 1 1 100.00
edn_csr_rw 2.000s 22.010us 1 1 100.00
edn_csr_aliasing 1.000s 40.225us 1 1 100.00
edn_same_csr_outstanding 2.000s 33.741us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 2.000s 18.291us 1 1 100.00
edn_csr_rw 2.000s 22.010us 1 1 100.00
edn_csr_aliasing 1.000s 40.225us 1 1 100.00
edn_same_csr_outstanding 2.000s 33.741us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 11.000s 3112.486us 1 1 100.00
edn_tl_intg_err 3.000s 74.713us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 44.428us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 39.529us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 11.000s 3112.486us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 11.000s 3112.486us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 11.000s 3112.486us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 11.000s 3112.486us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 39.529us 1 1 100.00
edn_sec_cm 11.000s 3112.486us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 39.529us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.000s 74.713us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 112.000s 8972.716us 1 1 100.00