Simulation Results: edn/edn1

 
16/09/2026 15:31:42 DVSim: v1.53.0 sha: aecc39b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.72 %
  • code
  • 82.06 %
  • assert
  • 98.70 %
  • func
  • 79.41 %
  • line
  • 98.18 %
  • branch
  • 93.29 %
  • cond
  • 88.00 %
  • toggle
  • 86.52 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.040s 15.778us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.970s 15.095us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.090s 35.802us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.500s 307.633us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.210s 47.346us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.300s 24.670us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.090s 35.802us 1 1 100.00
edn_csr_aliasing 1.210s 47.346us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.480s 66.580us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.480s 66.580us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.480s 66.580us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.130s 28.852us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.410s 43.183us 1 1 100.00
errs 1 1 100.00
edn_err 1.110s 94.963us 1 1 100.00
disable 2 2 100.00
edn_disable 1.010s 40.077us 1 1 100.00
edn_disable_auto_req_mode 1.410s 47.436us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.140s 1139.285us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.910s 42.727us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.070s 13.761us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.460s 711.063us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.460s 711.063us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.970s 15.095us 1 1 100.00
edn_csr_rw 1.090s 35.802us 1 1 100.00
edn_csr_aliasing 1.210s 47.346us 1 1 100.00
edn_same_csr_outstanding 1.590s 178.367us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.970s 15.095us 1 1 100.00
edn_csr_rw 1.090s 35.802us 1 1 100.00
edn_csr_aliasing 1.210s 47.346us 1 1 100.00
edn_same_csr_outstanding 1.590s 178.367us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.510s 205.750us 1 1 100.00
edn_tl_intg_err 1.890s 63.930us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.140s 149.106us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.410s 43.183us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.510s 205.750us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.510s 205.750us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.510s 205.750us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.510s 205.750us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.410s 43.183us 1 1 100.00
edn_sec_cm 3.510s 205.750us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.410s 43.183us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.890s 63.930us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 40.220s 3160.220us 1 1 100.00