Simulation Results: entropy_src/rng_16bits

 
16/09/2026 15:31:42 DVSim: v1.53.0 sha: aecc39b json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 70.81 %
  • code
  • 83.15 %
  • assert
  • 74.06 %
  • func
  • 55.21 %
  • block
  • 94.22 %
  • line
  • 97.88 %
  • branch
  • 86.32 %
  • toggle
  • 52.56 %
  • FSM
  • 95.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 62.220us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 3.000s 101.789us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 17.510us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 13.000s 438.750us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 2.000s 18.272us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
entropy_src_csr_mem_rw_with_rand_reset 3.000s 171.665us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 17.510us 1 1 100.00
entropy_src_csr_aliasing 2.000s 18.272us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 62.220us 1 1 100.00
entropy_src_rng 135.000s 14033.937us 1 1 100.00
entropy_src_fw_ov 136.000s 13206.014us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 136.000s 13206.014us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 135.000s 14033.937us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 565.000s 14068.469us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 135.000s 14033.937us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 135.000s 14033.937us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 135.000s 14033.937us 1 1 100.00
entropy_src_intr 3.000s 26.915us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 135.000s 14033.937us 1 1 100.00
entropy_src_functional_alerts 8.000s 1395.368us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 455.000s 14200.081us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 3.000s 115.250us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 4.000s 31.939us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 85.175us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 65.842us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 6.000s 93.702us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 6.000s 93.702us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 3.000s 101.789us 1 1 100.00
entropy_src_csr_rw 2.000s 17.510us 1 1 100.00
entropy_src_csr_aliasing 2.000s 18.272us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 687.799us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 3.000s 101.789us 1 1 100.00
entropy_src_csr_rw 2.000s 17.510us 1 1 100.00
entropy_src_csr_aliasing 2.000s 18.272us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 687.799us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 4.000s 103.396us 1 1 100.00
entropy_src_tl_intg_err 6.000s 964.409us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 135.000s 14033.937us 1 1 100.00
entropy_src_cfg_regwen 3.000s 37.993us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 135.000s 14033.937us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 135.000s 14033.937us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 135.000s 14033.937us 1 1 100.00
entropy_src_fw_ov 136.000s 13206.014us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 115.250us 1 1 100.00
entropy_src_sec_cm 4.000s 103.396us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 115.250us 1 1 100.00
entropy_src_sec_cm 4.000s 103.396us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 135.000s 14033.937us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 115.250us 1 1 100.00
entropy_src_sec_cm 4.000s 103.396us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 115.250us 1 1 100.00
entropy_src_sec_cm 4.000s 103.396us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 3.000s 115.250us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 8.000s 1395.368us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 6.000s 964.409us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 442.000s 13019.906us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 27.000s 3793.509us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1661) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.alert_test 1 test run
entropy_src_stress_all_with_rand_reset 92629055368985654211271174000455506433721171828067573242188191660349670801061 122
UVM_INFO @ 3793508778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---