| V1 |
|
100.00% |
| V2 |
|
88.24% |
| V2S |
|
100.00% |
| V3 |
|
50.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 4 | 4 | 100.00 | |||
| gpio_smoke | 1.980s | 84.690us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown | 1.410s | 510.129us | 1 | 1 | 100.00 | |
| gpio_smoke_en_cdc_prim | 2.300s | 181.100us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 1.320s | 131.239us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| gpio_csr_hw_reset | 1.100s | 261.861us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| gpio_csr_rw | 0.970s | 17.422us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| gpio_csr_bit_bash | 9.310s | 4746.391us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| gpio_csr_aliasing | 1.160s | 56.113us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| gpio_csr_mem_rw_with_rand_reset | 1.280s | 37.156us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| gpio_csr_rw | 0.970s | 17.422us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 1.160s | 56.113us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| direct_and_masked_out | 2 | 2 | 100.00 | |||
| gpio_random_dout_din | 1.440s | 92.277us | 1 | 1 | 100.00 | |
| gpio_random_dout_din_no_pullup_pulldown | 1.930s | 253.307us | 1 | 1 | 100.00 | |
| out_in_regs_read_write | 1 | 1 | 100.00 | |||
| gpio_dout_din_regs_random_rw | 1.030s | 118.771us | 1 | 1 | 100.00 | |
| gpio_interrupt_programming | 1 | 1 | 100.00 | |||
| gpio_intr_rand_pgm | 1.120s | 115.617us | 1 | 1 | 100.00 | |
| random_interrupt_trigger | 1 | 1 | 100.00 | |||
| gpio_rand_intr_trigger | 5.040s | 187.291us | 1 | 1 | 100.00 | |
| interrupt_and_noise_filter | 1 | 1 | 100.00 | |||
| gpio_intr_with_filter_rand_intr_event | 2.810s | 57.604us | 1 | 1 | 100.00 | |
| noise_filter_stress | 1 | 1 | 100.00 | |||
| gpio_filter_stress | 28.530s | 8807.629us | 1 | 1 | 100.00 | |
| regs_long_reads_and_writes | 1 | 1 | 100.00 | |||
| gpio_random_long_reg_writes_reg_reads | 9.400s | 3041.933us | 1 | 1 | 100.00 | |
| full_random | 1 | 1 | 100.00 | |||
| gpio_full_random | 1.480s | 412.319us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| gpio_stress_all | 19.100s | 4508.579us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| gpio_alert_test | 0.910s | 81.272us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| gpio_intr_test | 0.900s | 27.741us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 2.860s | 444.975us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 2.860s | 444.975us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 3 | 4 | 75.00 | |||
| gpio_csr_rw | 0.970s | 17.422us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 1.430s | 92.657us | 0 | 1 | 0.00 | |
| gpio_csr_aliasing | 1.160s | 56.113us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 1.100s | 261.861us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 3 | 4 | 75.00 | |||
| gpio_csr_rw | 0.970s | 17.422us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 1.430s | 92.657us | 0 | 1 | 0.00 | |
| gpio_csr_aliasing | 1.160s | 56.113us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 1.100s | 261.861us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| gpio_tl_intg_err | 2.510s | 143.088us | 1 | 1 | 100.00 | |
| gpio_sec_cm | 1.150s | 43.804us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| gpio_tl_intg_err | 2.510s | 143.088us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| straps_data | 1 | 1 | 100.00 | |||
| gpio_rand_straps | 0.880s | 26.192us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| gpio_stress_all_with_rand_reset | 18.360s | 4771.506us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| gpio_inp_prd_cnt | 0.920s | 19.648us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (gpio_scoreboard.sv:243) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 1 test run | |||
| gpio_stress_all | 82328626867457002352143934019114853915157790372337299339036018961813588230904 | 582 |
UVM_INFO @ 4508578638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* | 1 test run | |||
| gpio_stress_all_with_rand_reset | 8961363123798220330721978910049336580692523080762614471647103279753314908181 | 271 |
UVM_INFO @ 4771505607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:660) [gpio_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch | 1 test run | |||
| gpio_same_csr_outstanding | 12226310282669585121917033508372337544262792358728993951823505077817266524275 | 83 |
UVM_INFO @ 92657304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|