Simulation Results: hmac

 
16/09/2026 15:31:42 DVSim: v1.53.0 sha: aecc39b json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 69.80 %
  • code
  • 83.32 %
  • assert
  • 96.96 %
  • func
  • 29.13 %
  • block
  • 97.65 %
  • line
  • 98.44 %
  • branch
  • 94.11 %
  • toggle
  • 45.89 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 10.000s 895.644us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 80.981us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 30.971us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 7.000s 520.307us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.000s 80.782us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.000s 170.956us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 30.971us 1 1 100.00
hmac_csr_aliasing 3.000s 80.782us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 160.000s 44273.960us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 3.000s 52.931us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 16.000s 239.634us 1 1 100.00
hmac_test_sha384_vectors 31.000s 320.411us 1 1 100.00
hmac_test_sha512_vectors 36.000s 640.793us 1 1 100.00
hmac_test_hmac256_vectors 14.000s 1442.758us 1 1 100.00
hmac_test_hmac384_vectors 19.000s 903.951us 1 1 100.00
hmac_test_hmac512_vectors 19.000s 484.369us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 10.000s 926.764us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 2.000s 24.860us 1 1 100.00
error 1 1 100.00
hmac_error 99.000s 4370.835us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 153.000s 24334.719us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 10.000s 895.644us 1 1 100.00
hmac_long_msg 160.000s 44273.960us 1 1 100.00
hmac_back_pressure 3.000s 52.931us 1 1 100.00
hmac_datapath_stress 2.000s 24.860us 1 1 100.00
hmac_burst_wr 10.000s 926.764us 1 1 100.00
hmac_stress_all 250.000s 196809.073us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 10.000s 895.644us 1 1 100.00
hmac_long_msg 160.000s 44273.960us 1 1 100.00
hmac_back_pressure 3.000s 52.931us 1 1 100.00
hmac_datapath_stress 2.000s 24.860us 1 1 100.00
hmac_wipe_secret 153.000s 24334.719us 1 1 100.00
hmac_test_sha256_vectors 16.000s 239.634us 1 1 100.00
hmac_test_sha384_vectors 31.000s 320.411us 1 1 100.00
hmac_test_sha512_vectors 36.000s 640.793us 1 1 100.00
hmac_test_hmac256_vectors 14.000s 1442.758us 1 1 100.00
hmac_test_hmac384_vectors 19.000s 903.951us 1 1 100.00
hmac_test_hmac512_vectors 19.000s 484.369us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 10.000s 895.644us 1 1 100.00
hmac_long_msg 160.000s 44273.960us 1 1 100.00
hmac_back_pressure 3.000s 52.931us 1 1 100.00
hmac_datapath_stress 2.000s 24.860us 1 1 100.00
hmac_burst_wr 10.000s 926.764us 1 1 100.00
hmac_error 99.000s 4370.835us 1 1 100.00
hmac_wipe_secret 153.000s 24334.719us 1 1 100.00
hmac_test_sha256_vectors 16.000s 239.634us 1 1 100.00
hmac_test_sha384_vectors 31.000s 320.411us 1 1 100.00
hmac_test_sha512_vectors 36.000s 640.793us 1 1 100.00
hmac_test_hmac256_vectors 14.000s 1442.758us 1 1 100.00
hmac_test_hmac384_vectors 19.000s 903.951us 1 1 100.00
hmac_test_hmac512_vectors 19.000s 484.369us 1 1 100.00
hmac_stress_all 250.000s 196809.073us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 250.000s 196809.073us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 2.000s 21.695us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 108.857us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.000s 66.379us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.000s 66.379us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 80.981us 1 1 100.00
hmac_csr_rw 1.000s 30.971us 1 1 100.00
hmac_csr_aliasing 3.000s 80.782us 1 1 100.00
hmac_same_csr_outstanding 2.000s 59.757us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 80.981us 1 1 100.00
hmac_csr_rw 1.000s 30.971us 1 1 100.00
hmac_csr_aliasing 3.000s 80.782us 1 1 100.00
hmac_same_csr_outstanding 2.000s 59.757us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 251.161us 1 1 100.00
hmac_tl_intg_err 4.000s 682.923us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 4.000s 682.923us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 10.000s 895.644us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 4.000s 106.681us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 203.000s 17165.959us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 4.000s 179.618us 1 1 100.00