Simulation Results

Simulation Results: keymgr_dpe/darjeeling

16/09/2026 15:31:42 DVSim: v1.53.0 sha: aecc39b json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
65.71 %

code
82.47 %

assert
97.21 %

func
17.46 %

block
97.94 %

line
98.64 %

branch
93.29 %

toggle
56.39 %

FSM
81.54 %

Validation stages

V1		100.00%
V2		100.00%
V2S		100.00%

V1

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	keymgr_dpe_smoke	18.000s	982.576us	1	1	100.00
csr_hw_reset				1	1	100.00
	keymgr_dpe_csr_hw_reset	3.000s	57.859us	1	1	100.00
csr_rw				1	1	100.00
	keymgr_dpe_csr_rw	2.000s	133.620us	1	1	100.00
csr_bit_bash				1	1	100.00
	keymgr_dpe_csr_bit_bash	8.000s	505.596us	1	1	100.00
csr_aliasing				1	1	100.00
	keymgr_dpe_csr_aliasing	2.000s	76.075us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	keymgr_dpe_csr_mem_rw_with_rand_reset	1.000s	48.024us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	keymgr_dpe_csr_rw	2.000s	133.620us	1	1	100.00
	keymgr_dpe_csr_aliasing	2.000s	76.075us	1	1	100.00

V2

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
intr_test				1	1	100.00
	keymgr_dpe_intr_test	1.000s	19.468us	1	1	100.00
alert_test				1	1	100.00
	keymgr_dpe_alert_test	2.000s	58.785us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	keymgr_dpe_tl_errors	4.000s	283.764us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	keymgr_dpe_tl_errors	4.000s	283.764us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	keymgr_dpe_csr_hw_reset	3.000s	57.859us	1	1	100.00
	keymgr_dpe_csr_rw	2.000s	133.620us	1	1	100.00
	keymgr_dpe_csr_aliasing	2.000s	76.075us	1	1	100.00
	keymgr_dpe_same_csr_outstanding	3.000s	112.402us	1	1	100.00
tl_d_partial_access				4	4	100.00
	keymgr_dpe_csr_hw_reset	3.000s	57.859us	1	1	100.00
	keymgr_dpe_csr_rw	2.000s	133.620us	1	1	100.00
	keymgr_dpe_csr_aliasing	2.000s	76.075us	1	1	100.00
	keymgr_dpe_same_csr_outstanding	3.000s	112.402us	1	1	100.00

V2S

4/4 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	keymgr_dpe_sec_cm	12.000s	817.510us	1	1	100.00
	keymgr_dpe_tl_intg_err	6.000s	230.958us	1	1	100.00
shadow_reg_update_error				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	206.971us	1	1	100.00
shadow_reg_read_clear_staged_value				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	206.971us	1	1	100.00
shadow_reg_storage_error				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	206.971us	1	1	100.00
shadowed_reset_glitch				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	206.971us	1	1	100.00
shadow_reg_update_error_with_csr_rw				1	1	100.00
	keymgr_dpe_shadow_reg_errors_with_csr_rw	5.000s	101.396us	1	1	100.00
prim_count_check				1	1	100.00
	keymgr_dpe_sec_cm	12.000s	817.510us	1	1	100.00
prim_fsm_check				1	1	100.00
	keymgr_dpe_sec_cm	12.000s	817.510us	1	1	100.00