Simulation Results: lc_ctrl/volatile_unlock_disabled

 
16/09/2026 15:31:42 DVSim: v1.53.0 sha: aecc39b json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.43 %
  • code
  • 89.58 %
  • assert
  • 96.69 %
  • func
  • 79.03 %
  • block
  • 95.94 %
  • line
  • 96.90 %
  • branch
  • 89.66 %
  • toggle
  • 78.91 %
  • FSM
  • 92.86 %
Validation stages
V1
100.00%
V2
73.33%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 47.455us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 23.168us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 78.981us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 121.144us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 119.931us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 81.309us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 78.981us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 119.931us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 252.565us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 21.910us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 57.581us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 2 7 28.57
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3.000s 57.581us 1 1 100.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 8.000s 510.602us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3601.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 2.000s 97.359us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 6.000s 783.830us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.000s 917.959us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 4.000s 419.164us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 52.182us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.000s 1807.477us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.000s 119.373us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 79.572us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 327.856us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 65.886us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.000s 646.791us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 50.663us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10804.268s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 37.284us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 120.502us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 120.502us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 23.168us 1 1 100.00
lc_ctrl_csr_rw 1.000s 78.981us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 119.931us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 33.252us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 23.168us 1 1 100.00
lc_ctrl_csr_rw 1.000s 78.981us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 119.931us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 33.252us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 252.716us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 89.675us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 89.675us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 252.565us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 252.716us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 252.716us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 252.716us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 252.716us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 252.716us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 252.716us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 252.716us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 252.716us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 8.000s 510.602us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 749.880us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 1771.332us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 1771.332us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 10 test runs
lc_ctrl_state_failure 102908219801804237768954507712334934847989703625898829032380123821628255805492 None
lc_ctrl_state_post_trans 13521547872652745375933125995113626273607828284857991820240347910011631404448 None
lc_ctrl_errors 51557128664237839086887785987148187282422788931544668852713158921417934533115 None
lc_ctrl_jtag_state_failure 64127177795604537196071409768603851503570287661592308210696951672653861707048 None
lc_ctrl_jtag_state_post_trans 44479435009156277315267044491647850415082845755408316497702559004114156629844 None
lc_ctrl_jtag_prog_failure 107792374056860201193907933755476608627419370596240601787117394872921393790840 None
lc_ctrl_jtag_errors 107041655136265018669453972582574440727803910818038159687599463366102693830841 None
lc_ctrl_sec_mubi 13799659837436432673417324096796626399905791461896411956224408105831166578850 None
lc_ctrl_stress_all 89954147869879863243593132004474296422958312642897764994542115004265985015070 None
lc_ctrl_stress_all_with_rand_reset 19705500023174250881278175442860171340001716499168627622038422946859684223192 None