Simulation Results: lc_ctrl/volatile_unlock_enabled

 
16/09/2026 15:31:42 DVSim: v1.53.0 sha: aecc39b json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.67 %
  • code
  • 90.46 %
  • assert
  • 96.83 %
  • func
  • 78.71 %
  • block
  • 96.44 %
  • line
  • 97.24 %
  • branch
  • 90.96 %
  • toggle
  • 83.17 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
73.33%
V2S
70.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 257.950us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 125.680us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 182.528us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 62.230us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 21.519us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 36.495us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 182.528us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 21.519us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3601.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 344.236us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 14.343us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3601.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 5.000s 3478.185us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
jtag_access 11 13 84.62
lc_ctrl_jtag_smoke 3.000s 1111.843us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.000s 1833.270us 1 1 100.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 7.000s 473.008us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.000s 2021.357us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 139.662us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 282.202us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 10.000s 1960.758us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.000s 172.604us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 48.487us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 490.631us 1 1 100.00
lc_ctrl_jtag_alert_test 1.000s 33.562us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 11.000s 2390.245us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 36.087us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10802.063s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 155.786us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 38.182us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 38.182us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 125.680us 1 1 100.00
lc_ctrl_csr_rw 1.000s 182.528us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 21.519us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 17.556us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 125.680us 1 1 100.00
lc_ctrl_csr_rw 1.000s 182.528us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 21.519us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 17.556us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 170.027us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 127.397us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 127.397us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 344.236us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 170.027us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 170.027us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 170.027us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 170.027us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 170.027us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 170.027us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 170.027us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 170.027us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 3478.185us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 10.000s 1833.270us 1 1 100.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.000s 558.448us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 320.126us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 320.126us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3601.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 10 test runs
lc_ctrl_state_failure 64631485520437589255206296894221704460248835649085898587251407931194788904309 None
lc_ctrl_state_post_trans 26504830208546384980719333660082236174140817023429881761875573892884194854189 None
lc_ctrl_prog_failure 57958073605811475655299423364336270874634118956459357287996143954790322622723 None
lc_ctrl_errors 80271229103774336589817687843211080786847115478634564190470076118415755215224 None
lc_ctrl_jtag_state_failure 70899967594852059831935335552856600918734493917287685148353650331048659956807 None
lc_ctrl_jtag_prog_failure 13706463291816810609799432680080113973766325031013628736807516507104230544456 None
lc_ctrl_jtag_errors 93892693450934121561021532550884741187570844339828156700626231068749971433355 None
lc_ctrl_sec_mubi 36606438797639245610394087009467242722707202098825840426841937970839754759911 None
lc_ctrl_stress_all 26063662119604550379777828451429452657755210654380374735156875789972245112488 None
lc_ctrl_stress_all_with_rand_reset 95553991506789708890201901061319777818845515603455196845510952933604181219736 None