Simulation Results: mbx

 
16/09/2026 15:31:42 DVSim: v1.53.0 sha: aecc39b json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.30 %
  • code
  • 88.68 %
  • assert
  • 98.00 %
  • func
  • 78.21 %
  • block
  • 96.50 %
  • line
  • 96.36 %
  • branch
  • 90.81 %
  • toggle
  • 78.87 %
Validation stages
V1
83.33%
V2
81.82%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 41.000s 6413.278us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 2.000s 103.346us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 53.924us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 5.000s 291.699us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 1.000s 36.023us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 2.000s 1.197us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 53.924us 1 1 100.00
mbx_csr_aliasing 1.000s 36.023us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 1 100.00
mbx_stress 60.000s 6168.796us 1 1 100.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 4.000s 108.803us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 20.000s 2598.568us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 20.000s 1554.968us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 21.483us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 17.134us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 3.002us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 3.002us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 2.000s 103.346us 1 1 100.00
mbx_csr_rw 1.000s 53.924us 1 1 100.00
mbx_csr_aliasing 1.000s 36.023us 1 1 100.00
mbx_same_csr_outstanding 2.000s 121.761us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 2.000s 103.346us 1 1 100.00
mbx_csr_rw 1.000s 53.924us 1 1 100.00
mbx_csr_aliasing 1.000s 36.023us 1 1 100.00
mbx_same_csr_outstanding 2.000s 121.761us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 3.000s 155.043us 1 1 100.00
mbx_sec_cm 1.000s 14.027us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:718) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 49869920672799404667020827978752649023528031780268292000798770326158532194896 85
TL item was: req: (cip_tl_seq_item@18504) { a_addr: 'h4591fa14 a_data: 'hd56c2a72 a_mask: 'h1 a_size: 'h0 a_param: 'h0 a_source: 'hdf a_opcode: 'h1 a_user: 'h267a3 d_param: 'h0 d_source: 'hdf d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h152a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 3002006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 11804208623448494102119693113652717204955659517528101561389970694917236660501 86
TL item was: req: (cip_tl_seq_item@17992) { a_addr: 'he883cab0 a_data: 'hf39deec3 a_mask: 'ha a_size: 'h2 a_param: 'h0 a_source: 'h2a a_opcode: 'h1 a_user: 'h247d0 d_param: 'h0 d_source: 'h2a d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 1196765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register 1 test run
mbx_stress_zero_delays 68193614544089989827521125422013791317168979698001216678890543183537076230183 154
UVM_INFO @ 108802634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---