Simulation Results: rom_ctrl/32kb

 
16/09/2026 15:31:42 DVSim: v1.53.0 sha: aecc39b json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 81.68 %
  • code
  • 79.08 %
  • assert
  • 97.09 %
  • func
  • 68.88 %
  • block
  • 77.99 %
  • line
  • 78.48 %
  • branch
  • 77.91 %
  • toggle
  • 83.75 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
77.78%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.000s 227.929us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.000s 58.255us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 2.000s 72.646us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.000s 91.684us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 54.876us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 2.000s 82.603us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 2.000s 72.646us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 54.876us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 165.331us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.000s 81.280us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 2.000s 38.736us 0 1 0.00
stress_all 0 1 0.00
rom_ctrl_stress_all 10801.000s 0.000us 0 1 0.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 3.000s 62.952us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.000s 73.532us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.000s 85.190us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.000s 85.190us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 58.255us 1 1 100.00
rom_ctrl_csr_rw 2.000s 72.646us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 54.876us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 63.003us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 58.255us 1 1 100.00
rom_ctrl_csr_rw 2.000s 72.646us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 54.876us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 63.003us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 7.000s 1699.626us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 69.000s 442.942us 1 1 100.00
rom_ctrl_tl_intg_err 17.000s 302.806us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 69.000s 442.942us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 69.000s 442.942us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 69.000s 442.942us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 69.000s 442.942us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.000s 227.929us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.000s 227.929us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.000s 227.929us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 17.000s 302.806us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 3.000s 62.952us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 7.000s 1699.626us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 69.000s 442.942us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 31.000s 1507.621us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
rom_ctrl_stress_all 109665245805412453792703893946931871127326731079351801975926131277304238273381 None
rom_ctrl_corrupt_sig_fatal_chk 82222145828539868225091155593090722477637721320944179609726157636740950314795 None
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 34187685613908096918440779376454829189240963656099373416737150720995221037427 88
UVM_INFO @ 38736409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:354) [scoreboard] Check failed item.d_data[i**+:*] == exp_data[i**+:*] (* [*] vs * [*]) TLUL ROM read data incorrect 1 test run
rom_ctrl_stress_all_with_rand_reset 54825527899637526743831181002384987196424404168688464702469599762440423574179 131
UVM_INFO @ 1507620611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---