Simulation Results: rom_ctrl/64kb

 
16/09/2026 15:31:42 DVSim: v1.53.0 sha: aecc39b json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.21 %
  • code
  • 79.45 %
  • assert
  • 97.38 %
  • func
  • 84.80 %
  • block
  • 78.32 %
  • line
  • 78.74 %
  • branch
  • 78.84 %
  • toggle
  • 84.05 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.000s 744.082us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.000s 93.090us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.000s 109.263us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.000s 495.649us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 65.368us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.000s 82.019us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.000s 109.263us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 65.368us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 164.108us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.000s 55.509us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 5.000s 339.452us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 9.000s 273.944us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 4.000s 63.017us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.000s 60.584us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 9.000s 694.750us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 9.000s 694.750us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 93.090us 1 1 100.00
rom_ctrl_csr_rw 3.000s 109.263us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 65.368us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 51.944us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 93.090us 1 1 100.00
rom_ctrl_csr_rw 3.000s 109.263us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 65.368us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 51.944us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.000s 91.117us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 142.000s 742.748us 1 1 100.00
rom_ctrl_tl_intg_err 55.000s 700.604us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 142.000s 742.748us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 142.000s 742.748us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 142.000s 742.748us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 142.000s 742.748us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.000s 744.082us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.000s 744.082us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.000s 744.082us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 55.000s 700.604us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 4.000s 63.017us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.000s 91.117us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 142.000s 742.748us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
rom_ctrl_corrupt_sig_fatal_chk 43855786444072878176674317293412593484420313916258605474360323752020747207922 None
rom_ctrl_stress_all_with_rand_reset 20980226303413991912439704543068677618901012657052767659673146414440008223507 None
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 86361355016607340803795680173787406043727908932006905851495883159462562758169 88
UVM_INFO @ 339451892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---