Simulation Results: rstmgr

 
16/09/2026 15:31:42 DVSim: v1.53.0 sha: aecc39b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.00 %
  • code
  • 99.25 %
  • assert
  • 98.35 %
  • func
  • 96.39 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.86 %
  • toggle
  • 99.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.670s 59.009us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.710s 93.191us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.110s 36.179us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 6.970s 235.128us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.200s 37.824us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.950s 94.849us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.110s 36.179us 1 1 100.00
rstmgr_csr_aliasing 1.200s 37.824us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 2.160s 148.494us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.460s 42.723us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.380s 59.765us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 6.990s 589.725us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 6.990s 589.725us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 6.990s 589.725us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 6.990s 589.725us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 15.640s 1964.153us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.220s 37.456us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.160s 52.728us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.160s 52.728us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.710s 93.191us 1 1 100.00
rstmgr_csr_rw 1.110s 36.179us 1 1 100.00
rstmgr_csr_aliasing 1.200s 37.824us 1 1 100.00
rstmgr_same_csr_outstanding 1.680s 49.490us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.710s 93.191us 1 1 100.00
rstmgr_csr_rw 1.110s 36.179us 1 1 100.00
rstmgr_csr_aliasing 1.200s 37.824us 1 1 100.00
rstmgr_same_csr_outstanding 1.680s 49.490us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 18.910s 3387.495us 1 1 100.00
rstmgr_tl_intg_err 6.490s 624.073us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 18.910s 3387.495us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 18.910s 3387.495us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 6.490s 624.073us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.720s 67.309us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 5.630s 472.745us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 3.450s 291.520us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 18.910s 3387.495us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.110s 36.179us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.110s 36.179us 1 1 100.00