Simulation Results: spi_host

 
16/09/2026 15:31:42 DVSim: v1.53.0 sha: aecc39b json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.50 %
  • code
  • 91.14 %
  • assert
  • 94.71 %
  • func
  • 88.66 %
  • block
  • 96.78 %
  • line
  • 98.54 %
  • branch
  • 92.95 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 43.000s 4623.995us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 58.990us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 33.435us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 80.596us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 15.080us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 26.094us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 33.435us 1 1 100.00
spi_host_csr_aliasing 2.000s 15.080us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 33.289us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 71.541us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 89.629us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 194.866us 1 1 100.00
spi_host_error_cmd 1.000s 17.164us 1 1 100.00
spi_host_event 23.000s 1679.600us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 25.412us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 25.412us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 25.412us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 293.000s 11660.883us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 5.000s 192.338us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 2.000s 29.498us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 25.412us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 25.412us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 43.000s 4623.995us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 43.000s 4623.995us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 12.000s 820.113us 1 1 100.00
spien 1 1 100.00
spi_host_spien 9.000s 2513.447us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 284.000s 20897.655us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 3.000s 148.043us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 194.866us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 25.291us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 49.719us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 100.246us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 100.246us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 58.990us 1 1 100.00
spi_host_csr_rw 1.000s 33.435us 1 1 100.00
spi_host_csr_aliasing 2.000s 15.080us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 64.654us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 58.990us 1 1 100.00
spi_host_csr_rw 1.000s 33.435us 1 1 100.00
spi_host_csr_aliasing 2.000s 15.080us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 64.654us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 511.208us 1 1 100.00
spi_host_sec_cm 1.000s 120.044us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 511.208us 1 1 100.00