Simulation Results: sram_ctrl/main

 
16/09/2026 15:31:42 DVSim: v1.53.0 sha: aecc39b json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 94.96 %
  • code
  • 94.24 %
  • assert
  • 97.83 %
  • func
  • 92.80 %
  • block
  • 93.40 %
  • line
  • 94.38 %
  • branch
  • 90.75 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 555.638us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 18.465us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 20.502us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 815.808us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 11.110us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 1953.045us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 20.502us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 11.110us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 144.000s 5799.858us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 139.000s 22021.093us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 25.000s 12127.411us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 208.000s 4400.145us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 165.000s 17070.974us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 12.000s 1980.853us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 25.000s 18876.994us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 46.000s 42743.508us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 717.672us 1 1 100.00
sram_ctrl_partial_access_b2b 189.000s 4767.908us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 5.000s 827.102us 1 1 100.00
sram_ctrl_throughput_w_partial_write 5.000s 2476.465us 1 1 100.00
sram_ctrl_throughput_w_readback 8.000s 2406.637us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 9.000s 922.065us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 360.629us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 4.000s 555.638us 1 1 100.00
sram_ctrl_partial_access 4.000s 717.672us 1 1 100.00
sram_ctrl_access_during_key_req 12.000s 1980.853us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 422.000s 215994.985us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 22.184us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 44.885us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 44.885us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 18.465us 1 1 100.00
sram_ctrl_csr_rw 1.000s 20.502us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 11.110us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 23.225us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 18.465us 1 1 100.00
sram_ctrl_csr_rw 1.000s 20.502us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 11.110us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 23.225us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 31.000s 29444.316us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 306.683us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 193.701us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 306.683us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 193.701us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 922.065us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 922.065us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 20.502us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 46.000s 42743.508us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 46.000s 42743.508us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 46.000s 42743.508us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 25.000s 18876.994us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 31.000s 29444.316us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 555.638us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 555.638us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 46.000s 42743.508us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 306.683us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 25.000s 18876.994us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 306.683us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 306.683us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 555.638us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 306.683us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 36.000s 1451.075us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 33226935744623759143594645178032260391601766166309555626895495781575562811976 None
sram_ctrl_mubi_enc_err 70063678587060390332655859390652371596234916054927689540509177839263329486438 None