Simulation Results: uart

 
16/09/2026 15:31:42 DVSim: v1.53.0 sha: aecc39b json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.15 %
  • code
  • 73.64 %
  • assert
  • 97.12 %
  • func
  • 90.69 %
  • block
  • 98.58 %
  • line
  • 99.24 %
  • branch
  • 97.24 %
  • toggle
  • 73.08 %
  • FSM
  • 25.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 3.000s 431.260us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 114.805us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 24.092us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.000s 47.047us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 85.864us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 21.990us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 24.092us 1 1 100.00
uart_csr_aliasing 1.000s 85.864us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 258.000s 100935.882us 1 1 100.00
parity 2 2 100.00
uart_smoke 3.000s 431.260us 1 1 100.00
uart_tx_rx 258.000s 100935.882us 1 1 100.00
parity_error 2 2 100.00
uart_intr 486.000s 85125.648us 1 1 100.00
uart_rx_parity_err 44.000s 22901.450us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 258.000s 100935.882us 1 1 100.00
uart_intr 486.000s 85125.648us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 25.000s 150451.145us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 25.000s 55409.603us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 41.000s 24022.560us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 486.000s 85125.648us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 486.000s 85125.648us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 486.000s 85125.648us 1 1 100.00
perf 1 1 100.00
uart_perf 132.000s 4497.498us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 5.000s 8115.544us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 5.000s 8115.544us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 4.000s 4357.256us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 4.000s 6533.255us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 9.000s 1358.354us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 7.000s 2947.231us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 360.000s 134490.380us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 379.000s 294082.485us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 36.958us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 2.000s 21.913us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 4.000s 654.906us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 4.000s 654.906us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 114.805us 1 1 100.00
uart_csr_rw 1.000s 24.092us 1 1 100.00
uart_csr_aliasing 1.000s 85.864us 1 1 100.00
uart_same_csr_outstanding 1.000s 40.114us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 114.805us 1 1 100.00
uart_csr_rw 1.000s 24.092us 1 1 100.00
uart_csr_aliasing 1.000s 85.864us 1 1 100.00
uart_same_csr_outstanding 1.000s 40.114us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 262.021us 1 1 100.00
uart_tl_intg_err 1.000s 53.089us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.000s 53.089us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 22.000s 2319.291us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:392) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_noise_filter 81546967893536262261056505353954328692246672225152485704809937886755240740091 83
UVM_ERROR @ 919933940 ps: (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 1013052332 ps: (uart_scoreboard.sv:376) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 1013052332 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 1467526556 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr