Simulation Results: aes/gcm_unmasked

 
17/09/2026 15:31:44 DVSim: v1.53.0 sha: 18abe52 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 85.44 %
  • code
  • 91.30 %
  • assert
  • 97.75 %
  • func
  • 67.28 %
  • block
  • 90.74 %
  • line
  • 92.74 %
  • branch
  • 83.68 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
100.00%
V2S
81.25%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 61.432us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 135.981us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 7.000s 90.943us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 3.000s 117.692us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 13.000s 1077.900us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 6.000s 61.133us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 100.794us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 3.000s 117.692us 1 1 100.00
aes_csr_aliasing 6.000s 61.133us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 135.981us 1 1 100.00
aes_config_error 3.000s 138.320us 1 1 100.00
aes_stress 3.000s 80.839us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 135.981us 1 1 100.00
aes_config_error 3.000s 138.320us 1 1 100.00
aes_stress 3.000s 80.839us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 80.839us 1 1 100.00
aes_b2b 4.000s 187.458us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 80.839us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 135.981us 1 1 100.00
aes_config_error 3.000s 138.320us 1 1 100.00
aes_stress 3.000s 80.839us 1 1 100.00
aes_alert_reset 3.000s 109.693us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 71.066us 1 1 100.00
aes_config_error 3.000s 138.320us 1 1 100.00
aes_alert_reset 3.000s 109.693us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 271.779us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 145.367us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 109.693us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 80.839us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 80.839us 1 1 100.00
aes_sideload 3.000s 90.040us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 130.105us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 12.000s 1005.040us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 69.266us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 4.000s 482.911us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 4.000s 482.911us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 7.000s 90.943us 1 1 100.00
aes_csr_rw 3.000s 117.692us 1 1 100.00
aes_csr_aliasing 6.000s 61.133us 1 1 100.00
aes_same_csr_outstanding 2.000s 68.449us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 7.000s 90.943us 1 1 100.00
aes_csr_rw 3.000s 117.692us 1 1 100.00
aes_csr_aliasing 6.000s 61.133us 1 1 100.00
aes_same_csr_outstanding 2.000s 68.449us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 3.000s 118.419us 0 1 0.00
fault_inject 1 3 33.33
aes_fi 3.000s 149.412us 0 1 0.00
aes_control_fi 2.000s 70.593us 1 1 100.00
aes_cipher_fi 61.000s 0.000us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 90.400us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 90.400us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 90.400us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 90.400us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 143.251us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 5.000s 2455.892us 1 1 100.00
aes_tl_intg_err 2.000s 142.377us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 142.377us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 109.693us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 90.400us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 90.400us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 135.981us 1 1 100.00
aes_stress 3.000s 80.839us 1 1 100.00
aes_alert_reset 3.000s 109.693us 1 1 100.00
aes_core_fi 2.000s 143.805us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 138.320us 1 1 100.00
aes_stress 3.000s 80.839us 1 1 100.00
aes_core_fi 2.000s 143.805us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 90.400us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 71.507us 1 1 100.00
aes_stress 3.000s 80.839us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 80.839us 1 1 100.00
aes_sideload 3.000s 90.040us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 71.507us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 71.507us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 71.507us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 71.507us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 71.507us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 80.839us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 80.839us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 149.412us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 3.000s 149.412us 0 1 0.00
aes_control_fi 2.000s 70.593us 1 1 100.00
aes_cipher_fi 61.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 182.128us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 149.412us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 3.000s 149.412us 0 1 0.00
aes_control_fi 2.000s 70.593us 1 1 100.00
aes_cipher_fi 61.000s 0.000us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 61.000s 0.000us 0 1 0.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 149.412us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 149.412us 0 1 0.00
aes_control_fi 2.000s 70.593us 1 1 100.00
aes_ctr_fi 2.000s 182.128us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 149.412us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 3.000s 149.412us 0 1 0.00
aes_control_fi 2.000s 70.593us 1 1 100.00
aes_cipher_fi 61.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 182.128us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 109.693us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 3.000s 149.412us 0 1 0.00
aes_control_fi 2.000s 70.593us 1 1 100.00
aes_cipher_fi 61.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 182.128us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 3.000s 149.412us 0 1 0.00
aes_control_fi 2.000s 70.593us 1 1 100.00
aes_cipher_fi 61.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 182.128us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 149.412us 0 1 0.00
aes_control_fi 2.000s 70.593us 1 1 100.00
aes_ctr_fi 2.000s 182.128us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 149.412us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 3.000s 149.412us 0 1 0.00
aes_control_fi 2.000s 70.593us 1 1 100.00
aes_cipher_fi 61.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 18.108us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 2506971895429796540051280333399191234505427135531117199964812931323369962077 1299
UVM_INFO @ 118418641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 87963519983522279012398126069322781468294081052443100851231880367358705201515 2294
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 1
----| Expected corrupted: 0
Job timed out after * minutes 1 test run
aes_cipher_fi 27548624264363639069318420600726601898829919864798300697863796151125942412873 None
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 72584161242544117523475930514970597514484721252481725132969267076608554370795 167
UVM_INFO @ 18108178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---