Simulation Results: alert_handler

 
17/09/2026 15:31:44 DVSim: v1.53.0 sha: 18abe52 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.71 %
  • code
  • 91.70 %
  • assert
  • 98.38 %
  • func
  • 79.04 %
  • line
  • 99.76 %
  • branch
  • 98.13 %
  • cond
  • 90.80 %
  • toggle
  • 90.76 %
  • FSM
  • 79.03 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 31.020s 2318.332us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 8.220s 151.325us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 8.070s 146.398us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 754.820s 19088.991us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 139.540s 1748.986us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 7.620s 1052.292us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 8.070s 146.398us 1 1 100.00
alert_handler_csr_aliasing 139.540s 1748.986us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 111.540s 8243.144us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 37.970s 918.992us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 3041.450s 486971.150us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 20.780s 965.623us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 31.020s 2318.332us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 32.710s 1124.105us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 33.810s 2272.664us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 134.610s 3331.586us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 1010.790s 11641.762us 1 1 100.00
alert_handler_lpg_stub_clk 1441.240s 61415.242us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1889.350s 140303.690us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 18.280s 1013.601us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 3.340s 579.545us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.640s 60.881us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 14.720s 322.766us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 14.720s 322.766us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 8.220s 151.325us 1 1 100.00
alert_handler_csr_rw 8.070s 146.398us 1 1 100.00
alert_handler_csr_aliasing 139.540s 1748.986us 1 1 100.00
alert_handler_same_csr_outstanding 11.210s 1067.851us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 8.220s 151.325us 1 1 100.00
alert_handler_csr_rw 8.070s 146.398us 1 1 100.00
alert_handler_csr_aliasing 139.540s 1748.986us 1 1 100.00
alert_handler_same_csr_outstanding 11.210s 1067.851us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 204.440s 11388.310us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 204.440s 11388.310us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 204.440s 11388.310us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 204.440s 11388.310us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 711.980s 5019.531us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 19.570s 1239.397us 1 1 100.00
alert_handler_tl_intg_err 3.810s 131.624us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 3.810s 131.624us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 204.440s 11388.310us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 31.020s 2318.332us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 31.020s 2318.332us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 31.020s 2318.332us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 31.020s 2318.332us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 20.780s 965.623us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1010.790s 11641.762us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 20.780s 965.623us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 3041.450s 486971.150us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 3041.450s 486971.150us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 19.570s 1239.397us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 19.570s 1239.397us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 19.570s 1239.397us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 19.570s 1239.397us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 19.570s 1239.397us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 19.570s 1239.397us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 19.570s 1239.397us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 19.570s 1239.397us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 19.570s 1239.397us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 33.510s 923.368us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 87708892172402822818454523738259094230043896374738222183009545150770037767671 176
UVM_INFO @ 1013600510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 18595476142319471006296787557797687246276029603422253484585832760935584988595 95
UVM_INFO @ 923368480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---