Simulation Results: edn/edn1

 
17/09/2026 15:31:44 DVSim: v1.53.0 sha: 18abe52 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.23 %
  • code
  • 83.11 %
  • assert
  • 97.92 %
  • func
  • 80.67 %
  • line
  • 98.10 %
  • branch
  • 93.51 %
  • cond
  • 89.69 %
  • toggle
  • 87.68 %
  • FSM
  • 46.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.020s 21.796us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.200s 20.369us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.940s 107.613us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.600s 2647.341us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.040s 38.758us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.930s 146.005us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.940s 107.613us 1 1 100.00
edn_csr_aliasing 1.040s 38.758us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.700s 49.906us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.700s 49.906us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.700s 49.906us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.270s 20.177us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.460s 27.939us 1 1 100.00
errs 1 1 100.00
edn_err 1.310s 20.103us 1 1 100.00
disable 2 2 100.00
edn_disable 0.930s 13.094us 1 1 100.00
edn_disable_auto_req_mode 1.450s 113.069us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.420s 602.894us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.070s 24.426us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.120s 127.769us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.420s 446.751us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.420s 446.751us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.200s 20.369us 1 1 100.00
edn_csr_rw 0.940s 107.613us 1 1 100.00
edn_csr_aliasing 1.040s 38.758us 1 1 100.00
edn_same_csr_outstanding 1.390s 39.892us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.200s 20.369us 1 1 100.00
edn_csr_rw 0.940s 107.613us 1 1 100.00
edn_csr_aliasing 1.040s 38.758us 1 1 100.00
edn_same_csr_outstanding 1.390s 39.892us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.140s 788.744us 1 1 100.00
edn_tl_intg_err 1.820s 155.310us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.100s 27.326us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.460s 27.939us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.140s 788.744us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.140s 788.744us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.140s 788.744us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.140s 788.744us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.460s 27.939us 1 1 100.00
edn_sec_cm 5.140s 788.744us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.460s 27.939us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.820s 155.310us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 23.580s 1135.072us 1 1 100.00