Simulation Results: entropy_src/rng_16bits

 
17/09/2026 15:31:44 DVSim: v1.53.0 sha: 18abe52 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 71.34 %
  • code
  • 82.89 %
  • assert
  • 74.06 %
  • func
  • 57.06 %
  • block
  • 94.21 %
  • line
  • 97.86 %
  • branch
  • 86.29 %
  • toggle
  • 52.61 %
  • FSM
  • 94.79 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 3.000s 19.787us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 3.000s 226.563us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 16.298us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 25.000s 3807.697us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 2.000s 56.003us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
entropy_src_csr_mem_rw_with_rand_reset 2.000s 85.872us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 16.298us 1 1 100.00
entropy_src_csr_aliasing 2.000s 56.003us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 3.000s 19.787us 1 1 100.00
entropy_src_rng 252.000s 13089.687us 1 1 100.00
entropy_src_fw_ov 476.000s 14074.420us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 476.000s 14074.420us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 252.000s 13089.687us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 772.000s 14041.323us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 252.000s 13089.687us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 252.000s 13089.687us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 252.000s 13089.687us 1 1 100.00
entropy_src_intr 26.000s 1861.967us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 252.000s 13089.687us 1 1 100.00
entropy_src_functional_alerts 9.000s 362.337us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 153.000s 15221.212us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 79.830us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 5.000s 217.302us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 40.859us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 3.000s 67.306us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 5.000s 75.136us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 5.000s 75.136us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 3.000s 226.563us 1 1 100.00
entropy_src_csr_rw 2.000s 16.298us 1 1 100.00
entropy_src_csr_aliasing 2.000s 56.003us 1 1 100.00
entropy_src_same_csr_outstanding 4.000s 46.476us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 3.000s 226.563us 1 1 100.00
entropy_src_csr_rw 2.000s 16.298us 1 1 100.00
entropy_src_csr_aliasing 2.000s 56.003us 1 1 100.00
entropy_src_same_csr_outstanding 4.000s 46.476us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 3.000s 57.211us 1 1 100.00
entropy_src_tl_intg_err 4.000s 407.385us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 252.000s 13089.687us 1 1 100.00
entropy_src_cfg_regwen 7.000s 66.875us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 252.000s 13089.687us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 252.000s 13089.687us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 252.000s 13089.687us 1 1 100.00
entropy_src_fw_ov 476.000s 14074.420us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 79.830us 1 1 100.00
entropy_src_sec_cm 3.000s 57.211us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 79.830us 1 1 100.00
entropy_src_sec_cm 3.000s 57.211us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 252.000s 13089.687us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 79.830us 1 1 100.00
entropy_src_sec_cm 3.000s 57.211us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 79.830us 1 1 100.00
entropy_src_sec_cm 3.000s 57.211us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 79.830us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 9.000s 362.337us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 4.000s 407.385us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 503.000s 14075.871us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 26.000s 3166.613us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1661) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_lo_threshold 1 test run
entropy_src_stress_all_with_rand_reset 62686519197830314974832155880766275987825524759966196171414341110733660933328 126
UVM_INFO @ 3166613457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---