Simulation Results: hmac

 
17/09/2026 15:31:44 DVSim: v1.53.0 sha: 18abe52 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 69.88 %
  • code
  • 83.19 %
  • assert
  • 97.17 %
  • func
  • 29.28 %
  • block
  • 97.46 %
  • line
  • 98.39 %
  • branch
  • 93.64 %
  • toggle
  • 45.89 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 2.000s 92.428us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 16.299us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 42.368us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 15.000s 1134.933us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.000s 56.647us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 65.395us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 42.368us 1 1 100.00
hmac_csr_aliasing 2.000s 56.647us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 72.000s 17076.246us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 114.000s 13902.629us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 15.000s 242.455us 1 1 100.00
hmac_test_sha384_vectors 39.000s 309.896us 1 1 100.00
hmac_test_sha512_vectors 41.000s 561.546us 1 1 100.00
hmac_test_hmac256_vectors 14.000s 297.326us 1 1 100.00
hmac_test_hmac384_vectors 15.000s 376.682us 1 1 100.00
hmac_test_hmac512_vectors 18.000s 1046.776us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 25.000s 1644.573us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 294.000s 32345.052us 1 1 100.00
error 1 1 100.00
hmac_error 155.000s 12742.151us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 6.000s 598.553us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 2.000s 92.428us 1 1 100.00
hmac_long_msg 72.000s 17076.246us 1 1 100.00
hmac_back_pressure 114.000s 13902.629us 1 1 100.00
hmac_datapath_stress 294.000s 32345.052us 1 1 100.00
hmac_burst_wr 25.000s 1644.573us 1 1 100.00
hmac_stress_all 425.000s 123003.495us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 2.000s 92.428us 1 1 100.00
hmac_long_msg 72.000s 17076.246us 1 1 100.00
hmac_back_pressure 114.000s 13902.629us 1 1 100.00
hmac_datapath_stress 294.000s 32345.052us 1 1 100.00
hmac_wipe_secret 6.000s 598.553us 1 1 100.00
hmac_test_sha256_vectors 15.000s 242.455us 1 1 100.00
hmac_test_sha384_vectors 39.000s 309.896us 1 1 100.00
hmac_test_sha512_vectors 41.000s 561.546us 1 1 100.00
hmac_test_hmac256_vectors 14.000s 297.326us 1 1 100.00
hmac_test_hmac384_vectors 15.000s 376.682us 1 1 100.00
hmac_test_hmac512_vectors 18.000s 1046.776us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 2.000s 92.428us 1 1 100.00
hmac_long_msg 72.000s 17076.246us 1 1 100.00
hmac_back_pressure 114.000s 13902.629us 1 1 100.00
hmac_datapath_stress 294.000s 32345.052us 1 1 100.00
hmac_burst_wr 25.000s 1644.573us 1 1 100.00
hmac_error 155.000s 12742.151us 1 1 100.00
hmac_wipe_secret 6.000s 598.553us 1 1 100.00
hmac_test_sha256_vectors 15.000s 242.455us 1 1 100.00
hmac_test_sha384_vectors 39.000s 309.896us 1 1 100.00
hmac_test_sha512_vectors 41.000s 561.546us 1 1 100.00
hmac_test_hmac256_vectors 14.000s 297.326us 1 1 100.00
hmac_test_hmac384_vectors 15.000s 376.682us 1 1 100.00
hmac_test_hmac512_vectors 18.000s 1046.776us 1 1 100.00
hmac_stress_all 425.000s 123003.495us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 425.000s 123003.495us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 11.929us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 22.017us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.000s 348.191us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.000s 348.191us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 16.299us 1 1 100.00
hmac_csr_rw 1.000s 42.368us 1 1 100.00
hmac_csr_aliasing 2.000s 56.647us 1 1 100.00
hmac_same_csr_outstanding 3.000s 36.400us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 16.299us 1 1 100.00
hmac_csr_rw 1.000s 42.368us 1 1 100.00
hmac_csr_aliasing 2.000s 56.647us 1 1 100.00
hmac_same_csr_outstanding 3.000s 36.400us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 95.755us 1 1 100.00
hmac_tl_intg_err 5.000s 343.150us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 5.000s 343.150us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 2.000s 92.428us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.000s 30.535us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 22.000s 7548.513us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 4.000s 934.261us 1 1 100.00