Simulation Results

Simulation Results: i2c

17/09/2026 15:31:44 DVSim: v1.53.0 sha: 18abe52 json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
87.70 %

code
85.70 %

assert
96.19 %

func
81.22 %

block
95.98 %

line
95.31 %

branch
92.78 %

toggle
72.68 %

FSM
82.01 %

Validation stages

V1		100.00%
V2		80.49%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	369.000s	6272.452us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	9.000s	511.811us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.000s	26.184us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	6.000s	21.654us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	5.000s	333.854us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	24.094us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.000s	32.078us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	6.000s	21.654us	1	1	100.00
	i2c_csr_aliasing	2.000s	24.094us	1	1	100.00

33/41 passed

80.49 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	3.000s	289.797us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	1620.000s	4249.425us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	2307.000s	48909.105us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	1.000s	52.513us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3601.000s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	2289.000s	11437.275us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	3.000s	1630.908us	1	1	100.00
	i2c_host_fifo_fmt_empty	8.000s	578.497us	1	1	100.00
	i2c_host_fifo_reset_rx	25.000s	464.858us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	253.000s	3020.059us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	20.000s	1909.854us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	3.000s	320.340us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	5.000s	1109.163us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	3600.000s	0.000us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	8.000s	811.170us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	30.000s	5566.538us	1	1	100.00
	i2c_target_intr_smoke	8.000s	1034.642us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	196.394us	1	1	100.00
	i2c_target_fifo_reset_tx	3.000s	440.461us	1	1	100.00
target_fifo_full				1	3	33.33
	i2c_target_stress_wr	3601.000s	0.000us	0	1	0.00
	i2c_target_stress_rd	30.000s	5566.538us	1	1	100.00
	i2c_target_intr_stress_wr	3600.000s	0.000us	0	1	0.00
target_timeout				1	1	100.00
	i2c_target_timeout	13.000s	22239.551us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	543.000s	3388.806us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	8.000s	1156.686us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	13.000s	10605.648us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	6.000s	7931.910us	1	1	100.00
	i2c_target_fifo_watermarks_tx	3.000s	607.323us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	2307.000s	48909.105us	1	1	100.00
	i2c_host_perf_precise	7.000s	335.747us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	20.000s	1909.854us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.000s	77.040us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	6.000s	560.850us	1	1	100.00
	i2c_target_nack_acqfull_addr	4.000s	415.122us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	501.107us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	7.000s	480.298us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	5.000s	939.533us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	2.000s	30.166us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	17.302us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.000s	43.124us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.000s	43.124us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	26.184us	1	1	100.00
	i2c_csr_rw	6.000s	21.654us	1	1	100.00
	i2c_csr_aliasing	2.000s	24.094us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	23.808us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	26.184us	1	1	100.00
	i2c_csr_rw	6.000s	21.654us	1	1	100.00
	i2c_csr_aliasing	2.000s	24.094us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	23.808us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	3.000s	190.318us	1	1	100.00
	i2c_sec_cm	2.000s	128.843us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	3.000s	190.318us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	18.000s	1598.771us	1
target_error_intr				1
	i2c_target_unexp_stop	2.000s	135.627us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	13.000s	1260.905us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				4 test runs
	i2c_host_fifo_watermark	7412908492675292064053254788860180829318728090376122822902938368636226581109	None
	i2c_target_stress_wr	21051127722177175806068118174894189620547089964244761178767605924897547762629	None
	i2c_target_intr_stress_wr	103596447521384788348540798484504285692716672625201498550938438523451077319349	None
	i2c_target_stress_all	113404169344103536108219806654346249025515874863420257775437493132780150111538	None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				3 test runs
	i2c_host_error_intr	10324097405149882227017012369200086309357822449201825862531160383115580113326	121	UVM_INFO @ 289796778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	40336978378083602941141509608565969322000877947312217996933295555522262226986	129	UVM_INFO @ 4249424984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	99132540227197742624481262322951064066709438778461776608499529907773357525380	105	UVM_INFO @ 1260904996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	68192870660380209935167063261822888753965035390287565415696031776560928550224	93	UVM_INFO @ 1109162993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:680) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	16346638005926234632755628080574099625280657944425465671364338565688469190839	87	UVM_INFO @ 135626894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	110301856039843440848788589795326860902351516006025982900056477809854747910348	88	UVM_INFO @ 10605648076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	100150540571462811215004074008754946555073580692587770291953676536757581721794	106	UVM_INFO @ 1598771182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---